verilog mux not working

Question

I wanted to build a small code for 2*1 mux where the inputs come from different modules (to make it more practical), but I'm always getting output as High Impedence ('Z'). Any suggestions?

module  mux_using_assign(
  din_0      , // Mux first input
  din_1      , // Mux Second input
  sel        , // Select input
  mux_out      // Mux output
  );
  input din_0, din_1, sel ;
  output mux_out;
  wire  mux_out;
  assign mux_out = (sel) ? din_1 : din_0;

  endmodule //End Of Module mux


  module ip1();
  wire a;
  mux_using_assign dut1(.din_0(a));
  assign a = 1;
  endmodule


  module ip2();
  wire b;
  mux_using_assign dut1(.din_1(b));
  assign b = 0;
  endmodule



  module test();
  wire sel        ; // Select input
  wire mux_out;
  ip1 aa();    // tried commenting this and following line also
  ip2 bb();
  mux_using_assign dut1(.sel(sel),.mux_out(mux_out));
  assign sel=1;
  endmodule

score 0 · Accepted Answer · answered May 09 '15 at 13:43

0

The problem is that the dut1 instance in each module is a separate instance from the other modules. In other words, each of ip1, ip2, and test have their own dut1 muxer. You'll need to use input/output wires and link them all to a single mux_using_assign declaration.

answered May 09 '15 at 13:43

Drew McGowen

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jut want to confirm, providing same name to all instances of mux doesn't imply they are the same physical block? – user3185902 May 09 '15 at 13:46
so is there a way to do so using the syntax only, and not going for all the detailed wiring solution (looking for an easier way out), because this is just an experimental code for a bigger project. I have to implement an arbiter which takes input from different blocks and accesses memory output based on the selected input block. – user3185902 May 09 '15 at 13:50
Not that I'm aware of. Besides, the wiring solution isn't all that "detailed" - in fact, it's arguably better than what you're trying to do, as it separates interface from implementation. – Drew McGowen May 09 '15 at 13:51

verilog mux not working

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