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I'm stuck by this MASKMOVDQU instruction on page 902 of the intel x64 manual. I'm not quite sure how to change between the different register sizes in this instruction. It lists the default memory location as DS:DI/EDI/RDI but it also has 0x66 right in it's opcode. Do I remove that 0x66 and put 0x67/REX.W for EDI/RDI?

Also there's the VEX version of this instruction that's listed like this: 

VEX.128.66.0F.WIG F7 /r

How do I switch VEX instructions between 16/32/64 bit sizes?

Ryan Brown
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  • I'm not sure I understand what you are asking regarding the VEX instruction. If I recall correctly `66` is a non operation stub. The `DS:DI/EDI/RDI` just gives the 16, 32 & 64 bit registers showing where the instruction will be handled. I don't believe any change is required. – David C. Rankin May 07 '15 at 01:56
  • I think there's a way to switch between DS:DI, EDI, and RDI as the memory location but I don't know exactly how to do that – Ryan Brown May 07 '15 at 02:18

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The 66 is in the instruction to differentiate it from the MMX version MASKMOVQ. The 66 doesn't cancel the 67, just add it in the beginning. Note that the VEX encoded version doesn't even have the 66 0F, since those prefixes are embedded in the VEX itself, see section 2.3.1 Instruction Format:

Elimination of escape opcode byte (0FH), SIMD prefix byte (66H, F2H, F3H) via a compact bit field representation within the VEX prefix.

Also, section 2.3.5 The VEX Prefix:

Compaction of SIMD prefix: Legacy SSE instructions effectively use SIMD prefixes (66H, F2H, F3H) as an opcode extension field. VEX prefix encoding allows the functional capability of such legacy SSE instructions (operating on XMM registers, bits 255:128 of corresponding YMM unmodified) to be encoded using the VEX.pp field without the presence of any SIMD prefix. The VEX-encoded 128-bit instruction will zero-out bits 255:128 of the destination register. VEX-encoded instruction may have 128 bit vector length or 256 bits length.

Compaction of two-byte and three-byte opcode: More recently introduced legacy SSE instructions employ two and three-byte opcode. The one or two leading bytes are: 0FH, and 0FH 3AH/0FH 38H. The one-byte escape (0FH) and two-byte escape (0FH 3AH, 0FH 38H) can also be interpreted as an opcode extension field. The VEX.mmmmm field provides compaction to allow many legacy instruction to be encoded without the constant byte sequence, 0FH, 0FH 3AH, 0FH 38H. These VEX-encoded instruction may have 128 bit vector length or 256 bits length.

Jester
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  • This instruction is really confusing. What address size is default? I assume it's the 32-bit (EDI) and then you add 0x66 for 16-bit mode or REX.W for 64-bit? I see MASKMOVQ is almost the same thing, what happens if you change MASKMOVQ to 16-bit mode, wont that be the same exact instruction as the MASKMOVDQU in 32-bit mode? (66 0F F7) I'm sorry for being so dumb, it's just really confusing. As far as the VEX thing are you saying I should just add the prefix in front of the VEX or should it be in the VEX prefix itself? – Ryan Brown May 07 '15 at 23:42
  • The default address size depends on the current operating mode. In 64 bit mode that's 64 bits, in 32 bit 32 bit, etc. You can toggle between 16/32 and 32/64 using the 0x67. The 0x66 only toggles between mmx and sse, ie. MASKMOVQ and MASKMOVDQU. You can add the prefix, but it's highly unlikely you need that ... see [XY problem](http://xyproblem.info/). – Jester May 08 '15 at 00:06
  • Ah ty! I assume the 0x67 in front of the VEX prefix works too? – Ryan Brown May 08 '15 at 00:20
  • Yes it does, but I still find it unlikely you'd ever need it. – Jester May 08 '15 at 00:32