I have a VHDL package that defines a function (forward declaration) and a constant. The constant's value is calculated by that function, whose body is located in the package body.
As of now ModelSim/QuestaSim is the only tool that does not like this code. It needs 2 packages so the body was parsed before the constant declaration.
package test is
function mytest(param : boolean ) return boolean;
constant value : boolean := mytest(TRUE);
end package;
package body test is
function mytest(param : boolean ) return boolean is
begin
return not param;
end function;
end package body;
Is this not allowed in VHDL and other tools use relaxed parsing rules, or is that a ModelSim issue?