vectored input port driving output port of single bit net

Question

Why are these two codes not equivalent? I am checking the logical equivalence between the two, they are failing, what could be the error? Will it take it as width mismatch, or net driven by multiple drivers? I am using cadence LEC for formal verification

module driver (a, b);
  input [3:0] a;
  output wand b;

  assign b = a;
endmodule

module driver (a, b);
  input [3:0] a;
  output wand b;

  assign b = a[3];
  assign b = a[2];
  assign b = a[1];
  assign b = a[0];
endmodule

In the end, the answer to this question is going to be similar to your [previous](http://stackoverflow.com/questions/29555244/synthesis-of-wand-as-and-gate) one. — Qiu, Apr 16 '15 at 12:06

score 1 · Answer 1 · answered Apr 16 '15 at 20:02

assign b = a is equivalent to assign b = a[0]. The upper bits of a are out range for b.

Same reason with overflow. For example assign sum[3:0]=a[3:0]+b[3:0] if a=15 and b=2, sum will be 1 because there are not enough bits to represent 17 (17 mod (2^bitwidth(4)) = 1).

vectored input port driving output port of single bit net

1 Answers1