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Suppose we have the following situation: 2 CPU wtih write buffers and MESI is used as the cache coherence protocol. And we have one shared cache line between the CPUs:

CPU1 cache: |I|I|S|I|I|

CPU2 cache: |I|I|S|I|I|

Now CPU1 decides to modify the shared line. It puts the change record to its write buffer and sends invalidation message to CPU2. CPU2 receives it and sends an acknowledgment:

CPU1 cache: |I|I|S|I|I|, CPU1 write buffer: change for the 3rd cache line

CPU2 cache: |I|I|I|I|I|

Is it right that on receiving the acknowledgment CPU1 doesn't have to flush the write buffer and change the cache line state to M(modified)? If not than let's go further.

Suppose now CPU2 wants to read this cache line again. Should snooping CPU1 intercept this read request, and flush buffer->flush cache line->send the last value of the cache line to CPU2? Or it might ignore it and CPU2 would still have the old value by asking the RAM(which wasn't changed yet)?

Massimiliano
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ixSci
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1 Answers1

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In the standard MESI protocol, there is no acknowledgment of of invalidate transactions. In your example, the cache line transitions to the M state in CPU1 and the write is retired from the write buffer.

When CPU2 does a read, CPU1 writes out the modified line to memory. CPU2 can get the value either from CPU1 or from memory (only after CPU1's write completes). The write to memory is needed because there there is no O (Owned) state.

There are protocols like the Dragon protocol that do use a signal to indicate if a cache line is shared or not.

Craig S. Anderson
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  • I don't get on what event CPU1 has to change the state to _M_ and flush the buffer. Can you elaborate, please? – ixSci Apr 16 '15 at 07:23
  • The write buffer is in between the execution block and the rest of the memory hierarchy. The transition to _M_ and the invalidate happen when the write is taken out of the buffer and performed. Writes happen out of the write buffer so that the buffer doesn't fill and so that the write becomes visible to the other parts of the system. – Craig S. Anderson Apr 16 '15 at 07:31
  • So it happens simultaneously with the invalidation signal? CPU can't send an invalidation signal until it has purged the corresponding line out of the write buffer? If so then `StoreStore` barrier makes no sense since in this case MESI can't be violated in the write sequence, right? – ixSci Apr 16 '15 at 07:39
  • The transition to _M_ logically happens when the invalidate transaction happens on the bus. `StoreStore` affects how the behavior of multiple writes in the write buffer interact, not any single write. – Craig S. Anderson Apr 16 '15 at 07:50
  • Thank you, I finally got it. Only one last question: does CPU1 have to flush the write buffer(hence invalidating the cache line) if it gets read(or invalidation) request for the line from the CPU2(it is the last part of the original question)? – ixSci Apr 16 '15 at 07:57
  • Generally speaking, no flush is needed because the ordering of reads and writes between two processors is not specified. If the write is in the buffer, it has only happened with regard to the processor that did the write. However, a system could specify that a write is visible to other processors immediately, but that hurts performance. – Craig S. Anderson Apr 16 '15 at 08:04
  • So it means that CPU1 doesn't have to retire the write from the buffer on the read message from the CPU2, right? – ixSci Apr 16 '15 at 08:08