writing verilog module codes for up/down counter, 4to1 mux, pulsegen

Question

I'm fairly new to the world of creating verilog modules and I have to create a 4to1 mux, pulse generator, up/down counter, and a hex-to-7segment display. These are all later put into a toplevel module.

I tried to create the 7segement and pulse generator but I need help creating the 4to1 mux (i've only created 2to1 mux before) and the up/down counter.

this is the description on my lab paper.

pulse gen: used to control the time in which counter will increment or decrement. it uses the input named DELAU to determine length of time in-between each pulse output. each clock tick is counted. when # of counted clock ticks equal the delay input, a pulse is generated.

up/down counter: will increment or decrement an 8bit register each time pulse is received. when external switch from xilinx board is high(1) then counter will increment. switch is low(0) it will decrement the register. register count data is outputted to toplevel for LEDs and 7segement display.

4to1 mux: provide delay input to pulse gen. four inputs to mux will be hard-coded in top-level to provide a delay length of 0.5, 1, 1.5, and 2 seconds delay respectively. the 2bit select will come from 2 switches on xilinx board. from board, user will be able to switch choose the delay time the counter will count up or down.

so here is what i have so far. i really don't have much for the mux and updown counter. (could you also please check my pulsegen?)

4to1MUX

`timescale 1ns / 1ps
module mux4to1(sel,seg0,seg1,seg2,seg3,delay);
    input [1:0] sel;
    input seg0,seg1,seg2,seg3;
    output delay;
    wire delay;
    assign seg0 = 500000000;
    assign seg1 = 1000000000;
    assign seg2 = 1500000000;
    assign seg3 = 2000000000;
endmodule

UP/DOWN COUNTER

`timescale 1ns / 1ps
module updownCounter(updown,pulse,count);
    input [7:0] updown,
    input pulse;
     output [7:0] count;
     wire [7:0] count;

     (i'm not sure what goes here)
endmodule

PULSE GENERATOR

`timescale 1ns / 1ps
module pulsegen(clk,rst,delay,pulse);
    input [28:0] delay;
     output pulse;
     wire pulse;
     reg [28:0] count;

     always @(posedge clk, posedge rst)
        if (rst)
            count <= 28'b0;
        else if (pulse)
            count <= 28'b0;
        else
            count <= count + 28'b1;
     assign pulse = (count == delay);
endmodule

7SEGMENT DISPLAY

`timescale 1ns / 1ps
module sevenSegDis(hex,a,b,c,d,e,f,g);
    input [3:0] hex;
    output a,b,c,d,e,f,g;
     reg a,b,c,d,e,f,g;

     always@(*)
        case(hex)
            4'b0000: {a,b,c,d,e,f,g}= 7'b0000001;
            4'b0001: {a,b,c,d,e,f,g}= 7'b1001111;
            4'b0010: {a,b,c,d,e,f,g}= 7'b0010010;
            4'b0011: {a,b,c,d,e,f,g}= 7'b0000110;
            4'b0100: {a,b,c,d,e,f,g}= 7'b1001100;
            4'b0101: {a,b,c,d,e,f,g}= 7'b0100100;
            4'b0110: {a,b,c,d,e,f,g}= 7'b0100000;
            4'b0111: {a,b,c,d,e,f,g}= 7'b0001111;
            4'b1000: {a,b,c,d,e,f,g}= 7'b0000000;
            4'b1001: {a,b,c,d,e,f,g}= 7'b0000100;
            4'b1010: {a,b,c,d,e,f,g}= 7'b0001000;
            4'b1011: {a,b,c,d,e,f,g}= 7'b1100000;
            4'b1100: {a,b,c,d,e,f,g}= 7'b0110001;
            4'b1101: {a,b,c,d,e,f,g}= 7'b1000010;
            4'b1110: {a,b,c,d,e,f,g}= 7'b0110000;
            4'b1111: {a,b,c,d,e,f,g}= 7'b0111000;
            default: {a,b,c,d,e,f,g}= 7'b1110111;
        endcase
endmodule

score 0 · Answer 1 · answered Apr 15 '15 at 21:25

I think you slightly misunderstood the description of the multiplexer. You do not have to create the pulses inside of it, so the numbers 500000000, 1000000000, should not appear there.

Instead, the multiplexer should not care about what its inputs mean. It just has to connect one of them to the output, depending of the value of the select input. Like in the 7-segment decoder, you can use a case statement to model the multiplexer and it could look like this:

module mux4to1 (sel, seg0, seg1, seg2, seg3, delay);
  input [1:0] sel;
  input seg0, seg1, seg2, seg3;
  output delay;

  always @(*)
    case(sel)
    /* fill in the appropriate Verilog code which expresses this:
       if `sel` is 0 -> `delay` is `seg0`
       if `sel` is 1 -> `delay` is `seg1`
       and so on */
    endcase
endmodule

Your up/down counter needs an additional clock input. The updown input should be a single bit, not eight bits.

The code for the counter should look similar to that of the pulse generator. In every clock cycle, one of the following should happen:

if pulse is 0, the counter stays as it is
if pulse is 1 and updown is 1, the counter is increased by one
if pulse is 1 and updown is 0, the counter is decreased by one

Your pulse generator and 7-segment decoder seem to be okay.

writing verilog module codes for up/down counter, 4to1 mux, pulsegen

1 Answers1