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Is it possible to define a generic value at COMPILE time using Modelsim?

I need to compile a file that contains generate statements, which are turned off & on based on the value of my generic boolean.

I have unsuccessfully tried the following compile statement, where is_primary is the boolean variable name:

vcom -work work -is_primary=true file_name.vhd

I have found similar syntax for simulation (vsim), but I do not see a way to define a generic for vcom. Any suggestions?

AaronDanielson
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  • I don't know of any way for `vcom`, I do know for `vsim`. Why do you need that for vcom? It just seems like a bad design, generics should be set by the parent entity, not the compiler/synthesizer. Exception for the toplevel, since it has no parent... – Jonathan Drolet Apr 15 '15 at 19:35
  • I need to set the `generic` for `vcom` because I have a testbench .do file that compiles everything for test, including toplevel, and one of the modules that I need to simulate is capable of generating either a primary or secondary wiring configuration based on the boolean value of my generic 'is_primary'. After Modelsim testing, this design will be wrapped up as IP for use in Vivado, and the plan is to use the same IP block on both the primary & secondary sides, and just set the value of 'is_primary' to determine the wiring configuration. – AaronDanielson Apr 15 '15 at 21:35
  • I get the use of the generic, still don't get why it has to be set by `vcom`. Why don't you push that generic to the toplevel and use `vsim` to set it? – Jonathan Drolet Apr 15 '15 at 21:42
  • The generic is in fact available at the toplevel, but in my testbench, I need to simulate the primary & secondary side interactions, so I actually have 2 instantiations of toplevel inside my tb. I don't want 'is_primary' to be true for all components in my simulation. I thought I could compile toplevel twice, once with 'is_primary'=false, which would produce the two sides I need to simulate. `vsim` generics are defined globally for the simulation, no? I think my background in C might be confusing the definition of 'compile'. – AaronDanielson Apr 15 '15 at 22:07
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    If you instantiate twice your toplevel in the testbench, why don't you instantiate once with `is_primary` set to true and the second time set to false? It doesn't make sense to compile an entity with different parameters because both would have the same name, and the second compile would override the first, making impossible to reference both at the same time. – Jonathan Drolet Apr 16 '15 at 03:25
  • You're right. Good answer. I'll do that, thank you. So, back to the original question, it seems the answer is 'No, it's not possible to define a `generic` in the parameter list of `vcom`. – AaronDanielson Apr 16 '15 at 13:00

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A generic is just a constant that is passed into an entity through a generic list. You don't compile one toplevel and then compile the other toplevel, you compile a single toplevel and then the test bench with BOTH instantiations. You wire one up to true and the other up to false. Done.

U0 : entity toplevel generic map (is_primary => true) port map( insert ports here );

U1 : entity toplevel generic map (is_primary => false) port map( insert ports here );

Down in your hierarchy, however you cannot CHECK your generics until after elaboration. Run your sim 1 ps then go examine them.

Bob
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  • Is it correct that you have to bring "is_primary" all the way to the top level? It's not possible to set a generic variable at compile (synthesis) time to set some implementation option of a deeply buried entity? Not like verilog where it's easy to do that using #defines. – dsula Sep 01 '22 at 15:23