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It complains Input a<2:0> and Input b<2:0> is never used .The output is just displaying the concatenation of a[3] and b[3] (a = 1001, b = 1100).

module stone(a,b,rslt);
  input      [3:0] a,b;
  output reg [0:1] rslt;
  integer i;
  always @(a,b)
  begin
    for (i = 0; i <= 3; i = i + 1)
      rslt =  {a[i],b[i]};
  end
endmodule
Qiu
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Abdul Jalil Olawore
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  • What do you want as output? The single 8-bit value `10011100`; or `11` in the first clock cycle, then `01`, then `00`, and then `10`? – mkrieger1 Apr 12 '15 at 20:05
  • I see that you don't have a clock signal, so in case you want the second option, you need some sort of clock signal as an input to your module. – mkrieger1 Apr 12 '15 at 20:07
  • I just need 2 bit for every clock cycle nd ive tried using a clock its not working – Abdul Jalil Olawore Apr 14 '15 at 09:49
  • In order to attract more answers that are helpful to you, you should edit your question so it becomes more clear what exactly you want to do and what you have already tried (for example, how you have attempted to use a clock, and how that didn't give you the result you want). – mkrieger1 Apr 14 '15 at 10:38

1 Answers1

2

The for loop you are using is equivalent to the following code:

rslt = {a[0], b[0]};
rslt = {a[1], b[1]};
rslt = {a[2], b[2]};
rslt = {a[3], b[3]};

This means that in the end only the last statement has an effect and the first three do not.

mkrieger1
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