0

According to the riscv-gcc compiler we are generated the binary file. This binary file data are feeding to rocket chip through this signals. io_host_in_valid, input [15:0] io_host_in_bits

Here io_host_in_bits is 16-bit, so we are driving the 2-times for each instruction data in little-Endian mode. We are not getting any response from Rocket core (HTIF). How to simulate the Rocket core and if it is possible to simulate in Xilinx Vivado 2014 as well as debug the design. Can any one help me about this

Regards, Santhosh Kumar.

Santhosh Kumar
  • 25
  • 1
  • 3
  • 8

2 Answers2

1

For more information on the Rocket Chip infrastructure, I recommend checking out the slides and videos from the first RISC-V Bootcamp.

The Rocket Chip can be simulated/debugged in two different ways: C simulator and Verilog. For information on using these modes, please consult the Rocket Chip README.

user2548418
  • 1,531
  • 10
  • 17
  • We are trying to simulate design in verilog way. We are driving the valid instructions to HTIF but we are not getting any response from core. – Santhosh Kumar Apr 13 '15 at 05:37
  • Are you using the front-end server? Are you using the rocket chip repo's harness? – user2548418 Apr 14 '15 at 17:17
  • we are using rocket chip harness and we are driving the data to rocketcore through HTIF. we are trying to simulate the design in questa simulation. is it possible to do so ? could you please help by providing some inputs on this – Santhosh Kumar Apr 16 '15 at 08:35
  • The short answer is HTIF is a means of loading the processor's memory (including sending program binaries), not necessarily a way of feeding it instructions. You will want to use the Front-end Server (FESVR) or at least study its code to learn about HTIF is used. I posted the response from the mailing list as another answer. – user2548418 Apr 16 '15 at 16:43
  • In vcs_main.cc file we have vcs simulator routines. The vcs simulator will use DirectC so we have to change these routines into modelsim simulator compatible. Here we have vcs routines **vc_getScalar vc_putScalar vc_put4stVector vc_4stVectorRef** How to replace these routine with normal C++ logic. – Santhosh Kumar Jun 02 '15 at 11:39
  • For purely C++ emulation, you should use Rocket Chip's builtin emulator. It can produce VCD outputs, which are readable by any VCD reader including ModelSim. If you want to use Modelsim to simulate, yes, you will need to write a wrapper (harness). – user2548418 Jun 02 '15 at 20:48
  • Thanks for your reply, I have tried using the pure C++ emulation method and got a vcd dump file, however this file does not have all the signals and it is not possible to understand the interface requirement from the vcd dump.It is not have a timescale so it is not possible to figure out the exact frequency of operation though it may be cycle accurate and so does not help much. – Santhosh Kumar Jun 08 '15 at 07:04
  • Yes, the emulator is cycle accurate but it will not return a clock rate since the design has not been physically instantiated. Which signals are missing? For understanding the interface, we still recommend the other answer (http://stackoverflow.com/a/29681063/2548418) to this question. – user2548418 Jun 08 '15 at 23:45
1

Yunsup's response on the riscv-hw mailing list:

I would take a look at http://riscv.org/tutorial-hpca2015/riscv-rocket-chip-generator-tutorial-hpca2015.pdf for an overview of interfaces and the FPGA setup.

Here’s a link to our test bench we use to test the rocket chip: https://github.com/ucb-bar/rocket-chip/blob/master/vsrc/rocketTestHarness.v. I would take a look at the htif_tick function, where the implementation can be found here at https://github.com/ucb-bar/rocket-chip/blob/master/csrc/vcs_main.cc, which calls a method on htif_emulator_t (https://github.com/ucb-bar/rocket-chip/blob/master/csrc/htif_emulator.h), which is inherited from htif_pthread_t (https://github.com/riscv/riscv-fesvr/blob/master/fesvr/htif_pthread.cc). You should also take a look at https://github.com/riscv/riscv-fesvr/blob/master/fesvr/htif.cc.

The host interface (HostIO) doesn’t take instructions directly, it’s a port for the front-end server (https://github.com/riscv/riscv-fesvr/tree/master/fesvr) to access target memory and the core’s control and status registers (CSR).

Community
  • 1
  • 1
user2548418
  • 1,531
  • 10
  • 17
  • Thank you for valuable reply. Here i am working on the Questa simulator! so i have to use DPI or PLI Calls ? – Santhosh Kumar May 08 '15 at 11:27
  • Whatever simulator you use, you will need to make a harness. The harness should connect to the processor via HTIF and get programs from the FESVR. The Rocket Chip repository includes a C++ harness as well as a Verilog harness for VCS. – user2548418 May 08 '15 at 19:18