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I'm reading some technical reference of a DMA controller but I don't understand many things, it seems that I'm missing some points, I have no practical experience dealing directly with DMA but want to understand at least the theory.

In the document it is mentioned:

The DMA controller contains an instruction processing block that enables it to process program code that controls a DMA transfer.

So what's the purpose of that instruction processing block? who load instructions into it? I mean, if I write a driver to my device, then in order to transfer a big chunk of data from/to my device I should load the instructions to the DMA to do that? (is it the same bunch of instructions that I would feed the main processor with if there was no DMA?

The DMAC also contains an ARM AMBA and AXI master interface unit to fetch the program code from system memory into instruction cache. The DMA instruction execution engine executes the program code from its instruction cache and schedules read/write AXI instructions through the respective instruction queue.

I know what is AMBA and AXI but still. Is it the same as before? what is the program code, what its purpose? and if the DMA controller itself has the previous "instruction processing block" then what is the "instruction cache"? What is exactly "instruction execution engine"? is it like the cpu of the DMA?

These are the main things, I assume that after understanding them, other things would be more clear as well.

I'll appreciate any good answer and reference about the field since I didn't find much.

Bush
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  • I have no experience with this DMA controller. However, other *non-dedicated* DMA controllers have an *instruction processing block* which may do simple things like to increment a pointer. Ie, writing to a FIFO register versus traditional *array based* memory. The **IPU** maybe able to calculate different CRC and to schedule multiple DMA transfers. The DMA **IPU** needs to get it's code from some place. For a UART, you maybe able to put SDLC/HDLC framing inside the **IPU** for example. Typically the DMA is actually a very limited RISC CPU with a load/store unit to multiple ports. – artless noise Mar 31 '15 at 16:15
  • IPU = Instruction Processing Unit? So basically the DMA driver initialize the DMA controller by loading a set of limited RISC instructions into the DMA instructions block? – Bush Mar 31 '15 at 17:09
  • Yes, that is my guess by quickly perusing the information. The DMA engine is a small CPU probably with multiple buses [Harvard vs von Neumann](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka3839.html). For a dedicate DMA (ethernet, USB) they typically do not have this flexibility exposed. This is a more generic DMA engine so often you need some specialized repetitive stuff (CRC/Checksum, scatter/gather) which fits well as you transfer the data. Giving access to program the DMA engine code makes the engine fit with more use cases. – artless noise Mar 31 '15 at 17:38

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