Can anyone please explain this in a easier way?

Question

I had take up a computer organization course a year ago and now I have a follow up to it as 'Computer architecture' , I am using the 3rd edition of John Hennessy's book 'Quantitative approach to computer architecture', I went through the MIPS ISA but still need some help , can you explain this line of code in greater detail

Source code:

for(i=1000; i>0; i--)
    x[i] = x[i] + s;

Assembly code:

   Loop:      L.D         F0, 0(R1)          ; F0 = array element
              ADD.D       F4, F0, F2        ; add scalar
              S.D         F4, 0(R1)          ; store result
              DADDUI      R1, R1,# -8      ; decrement address pointer
              BNE         R1, R2, Loop    ; branch if R1 != R2

This is given as an example for loop unrolling to exploit ILP , I have a few doubts . I do get it that the array starts at Mem[0+R1] and goes backwards till Mem[R+8](as given in the text) , any reason for this or they just randomly took this location?

Also why use a DADDUI (unsigned ) when we are adding a signed number (-8) ?

Please give a detailed overview of this so that i can follow along the rest of the topics. Thanks

Your doubts don't seem to relate to ILP. Memory locations are arbitrarily chosen by the programmer, not the compiler. Particular instructions may be chosen arbitrarily as long as they get the job done. — Potatoswatter, Mar 29 '15 at 08:26
As i mentined my doubts lie with the MIPS code, new to it , not with ILP ,i assume DADDUI means the result won't become negative , not that it can't operate on negative numbers , am i correct? — Sainath S.R, Mar 29 '15 at 08:27
Neither. Probably it just avoids setting the negative flag bit. Refer to an ISA reference to learn about particular instructions. — Potatoswatter, Mar 29 '15 at 08:29

score 4 · Accepted Answer · edited Jun 20 '20 at 09:12

The memory accesses are performed to the addesses and in the order as specified by the loop in the source code.

The daddiu instruction is sufficient to perform such address arithmetic. The "negative" value accomplishes subtraction in two's-complement. Addresses are neither negative nor positive; they are just bit-patterns. Refer to an ISA reference to learn more about MIPS and instructions.

The 16-bit signed immediate is added to the 64-bit value in GPR rs and the 64-bit arithmetic result is placed into GPR rt . No Integer Overflow exception occurs under any circumstances.

…

The term “unsigned” in the instruction name is a misnomer; this operation is 64-bit modulo arithmetic that does not trap on overflow. It is appropriate for unsigned arithmetic such as address arithmetic, or integer arithmetic environments that ignore overflow, such as C language arithmetic.

The example is not optimized or unrolled. It's just a literal translation of the source.

Can anyone please explain this in a easier way?

1 Answers1