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EDIT1 okay i couldnt post a long comment(i am new to the website so please accept my apologies) so i am editing my earlier question. I have tried to implement multiplexing in 2 attempts:

-2nd attempt

-3rd attempt

in 2nd attempt i have tried to send the seven seg variables of each module to the module which is just one step ahead of it, and when they all reach the final top module i have multiplexed them...there is also a clock module which generates a clock for the units module(which makes units place change 2 times in a second) and a clock for multiplexing(multiplexing between each displays 500 times per second)...ofcourse i read that my board has a clock freq of 50M hertz, so these calculations for clocks are based on that figure...

in the 3rd comment i have done the same thing, in one single module. see the 2nd attempt first and then the 3rd one.

both give errors right after synthesis and lots of unfamiliar warnings.

EDIT 2

I have been able to synthesize and implement the program in attempt4(which i am not allowed to post since my reputation is low), using the save flag for variables, variables1 variables2 and variables3(which were giving warning of unused pins) but the program doesnt run on fpga...it simply shows the number 3777. also there are still warnings of "combinatorial loops" for some things that are related to some variables( i am sorry i am new to all this verilog thing) but you can see all of them in attempt 3 as well.

Mohammed Manzar
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    Can you add the relevant part of your source code. Also read http://stackoverflow.com/help/how-to-ask – Ortomala Lokni Mar 21 '15 at 15:40
  • One can not down your file because credentials are required! More comments: Xilinx ISE 13.2 is very outdated. Can you name your board and FPGA? I don't think there is any Xilinx FPGA board that allows you to drive 4 7-segment displays simultaneously. – Paebbels Mar 21 '15 at 16:07
  • From his dropbox download there's an image of his board, it's a Digilent Nexys2 from 2007, and it does indeed have four LED 7 segment displays. –  Mar 21 '15 at 17:49
  • If you look in the [Digilent Nexys2 Board Reference Manual](http://www.digilentinc.com/data/products/nexys2/nexys2_rm.pdf), page 5, figure 8 you'd find your LED digits have common cathodes and anode steering. Your nested hierarchy doesn't have a way of multiplexing those 4 digits cathodes (7 segments). It would seem easier to interconnect the 4 digits cathodes all in the same module instead of using a nested hierarchy. Read pages 4 through 6 of the Reference Manual. Your task1 assignment parameters aren't clear from what you provide. –  Mar 21 '15 at 20:00
  • i am very thankful to your support and quick replies, i have tried to implement what you have suggested in 2 seperate attempts, both have synthesized but are they give error when you click on implement design, kindly refer to my comment on the answer given by paebbels – Mohammed Manzar Mar 22 '15 at 16:36
  • actually i couldnt post a long comment so i have editited my origina question – Mohammed Manzar Mar 22 '15 at 16:48
  • See in the Stackoverflow Help Center [How do I ask a good question?](http://stackoverflow.com/help/how-to-ask) ( in particular "...also include the code in your question itself. Not everyone can access external sites, and the links may break over time"). Without the 4th attempt you won't get any meaningful help. Your 2nd/3rd attempts require login credentials as linked. See [How to create a Minimal, Complete, and Verifiable example](http://stackoverflow.com/help/mcve). Most of the zip file contents are likely irrelevant. Is this a school assignment? –  Mar 23 '15 at 05:20
  • yeah i am sorry i'll take care next time. I have successfully implemented and run the counter on board., it was a university assignment, if anyone wants the code then please let me know. – Mohammed Manzar Mar 24 '15 at 11:07
  • and thankyou for your answers, all of them. – Mohammed Manzar Mar 24 '15 at 11:08

1 Answers1

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You can not implement counters with loops. Neither can you implement cascaded counters with nested loops.

Writing HDL is not writing software! Please read a book or tutorial on VHDL or Verilog on how to design basic hardware circuits. There is also the Synthesis and Simulation Guide 14.4 - UG626 from Xilinx. Have a look at page 88.

Edit1:

Now it's possible to access your zip file without any dropbox credentials and I have looked into your project. Here are my comments on your code.

I'll number my bullets for better reference:

  1. Your project has 4 mostly identical ucf files. The difference is only in assigning different anode control signals to the same pin location. This will cause errors in post synthesis steps (assign multiple nets to one pin). Normally, simple projects have only one ucf file.
  2. The Nexsys 2 board has a 4 digit 7-segment display with common cathodes and switchable common anodes. In total these are 8+4 wires to control. A time multiplexing circuit is needed to switch at 25Hz < f < 1kHz through every digit of your 4-digit output vector.
  3. Choosing a nested hierarchy is not so good. One major drawback is the passing of many signals from every level to the topmost level for connecting them to the FPGA pins. I would suggest a top-level module and 4 counters on level one. The top-level module can also provide the time-multiplexing circuit and the binary to 7-seg encoding.
Paebbels
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  • The only place 'loop' appears in his source code are in his individual testbenches, for clock generation. The design is a nested hierarchy purported to implement the display of a units digit, a tens digit, a hundreds digit and a thousands digit. Your semantic analysis of his question only attacks the language of the question and does not address his problem (which isn't clearly stated). –  Mar 21 '15 at 19:12
  • @DavidKoontz Sorry, but the OP offered a link that needed credential to download the zip file. Now it's accessible and I will look into it. He also described 4 nested loops which do the counting, so without any source code there was no way to see what he had coded so far... – Paebbels Mar 21 '15 at 23:39
  • I modified the link so you don't need to login to dropbox. How can you answer without knowing the problem? –  Mar 21 '15 at 23:58
  • @DavidKoontz He described his problem. On the one hand he stated to use 'loops' to implement counters - ok that was a bad choice of words. On the other hand he reported only one active digit and all segments enlightened. That is in most cases cause by a wrong or missing anode control logic (time multiplexing module) - that's why I asked for the board's name and stated that it's not possible to drive all digits simultaneous. – Paebbels Mar 22 '15 at 00:18