Get constant output during clock cycles

Question

I want to change my out put when my input is changed but after this changes, my output will be constant during 4 clock cycles. After 4 clock cycles, if input is changed, out put will been changed with input. In conclusion, I want to wait during 4 clock cycles after there is a change in my output.

I can do it with a second clock but I do not want to use this way. How can I get the resut shown below?

I am using Quartus II 9.0 Web Edition.

Answer 1

You will need a 3-bit counter and a 1-bit register tied to your output signal. At every clk tick, and if the 3-bit counter is greater than 011, take the input and store in the 1-bit register. Reset the counter to 000.

Besides, if your 3-bit counter is not greater than 011, increment it.

So the 3-bit counter serves as delay to not to update the output with the input until 4 clocks have happened.

With this you can hopefully elaborate your own Verilog description.

Answer 2

You need a 2-bit mod 4 counter to generate the enable strobe for a 1-bit data register. The counter counts as normal from 00 to 11 and overflows. If counter equals 00 the data register is enabled to store the input value for the next 4 cycles.

Notes:

• Your timing diagram shows not the described behavior. The second high cycle on output is generated before the triggering rising edge of clock.
• If input is async to to clock, you need to synchronize it first to avoid metastability.
• Our (mcleod_ideafix's and mine) solutions generate a 1 cycle delay between input and output. If that is not tolerable, switch from Moore to Mealy model.