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im converting a verilog test bench to VHDL and need help understanding some parts as i am not familiar with verilog. 

initial begin 
ShiftEn <= 1'b1;
FillSel <= 1'b1;
DataIn_i <= 1'b0;
DataIn_q <= 1'b0;

repeat(16) @(posedge clk);
  DataIn_i <= 1'b1;
  DataIn_q <= 1'b1;
@(posedge clk);
  FillSel <= 1'b0;
  DataIn_i <= 1'b0;
  DataIn_q <= 1'b0;
end

Thanks in advance!

semiautomatic
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  • This is not a question. –  Feb 22 '15 at 17:52
  • possible duplicate of [VHDL equivalent for Verilog @(posedge clk)](http://stackoverflow.com/questions/28658363/vhdl-equivalent-for-verilog-posedge-clk) – dave_59 Feb 23 '15 at 04:22

1 Answers1

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Firstly, if you are already familiar with Verilog or VHDL, I would advise you not to learn another one. Though if you really need code translation, you should first check out Verilog syntax and if you haven't found anything, ask it here, because your question is not clear enough. To start with, posedge clk is a clause of making something when signal goes high (positive edge); 1'b1 means that you want to have binary number of 1 bit and make it high, 1'b0 means the same, but is made low.

There are a lot of information in the internet about Verilog so it is not really appropriate to ask for this kind of information. For example, try this one

Artūras Jonkus
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