I have a number of coefficients of type double, which should be stored on an FPGA as signed 16-bit numbers. For that I need to configure how many bits of the 16bit should be used for the fraction and how many for the integer part. So the idea is, that I search through my array with coefficients, take the integer part of it and calculate how many bits would be needed to represent it. I do this until the biggest coefficient.
This is my code up until now:
double value;
int value_intpart;
double value_array[] = {0.33333333333333333, 0.67676767676767676, -0.67676767676767777, 1.1111111111111111, 2.3654375346357653, -2.3658375346397653, 10.365437534635765};
for(int counter = 0; counter < 7; counter++)
{
value = value_array[counter];
value_intpart = floor(abs(value) + 1);
std::cout << "Value: " << value << std::endl;
if(abs(value) > max_coeff)
{
if(value >= -0.5 && value < 0.5)
bits = 0;
else
{
bits = ceil( log(value_intpart)/log(2) + 1 );
std::cout << "Value_intpart: " << value_intpart << " Log2: " << log(value_intpart)/log(2) << std::endl;
}
std::cout << "Bits: " << bits << std::endl;
max_coeff = value;
}
}
It gives me the following output:
Value: 0.333333
Bits: 0
Value: 0.676768
Value_intpart: 1 Log2: 0
Bits: 1
Value: -0.676768
Value_intpart: 1 Log2: 0
Bits: 1
Value: 1.11111
Value_intpart: 2 Log2: 1
Bits: 2
Value: 2.36544
Value_intpart: 3 Log2: 1.58496
Bits: 3
Value: -2.36584
Value_intpart: 3 Log2: 1.58496
Bits: 3
Value: 10.3654
Value_intpart: 11 Log2: 3.45943
Bits: 5
But I am not really sure about the effectivness of that code and if it is entirely correct. For example I found no other way as to check manually for the region from -0.5 until 0.5 (without 0.5). Could you give me some feedback to that code?