What is the result of synthesis?

Question

I'm trying to implement to gate as follows. But i'm not sure how does it synthesis to gate?

case 1

wire [3:0] A, B, C, D;  
always @(posedge CLK)
    begin
        C=B;
        B=A;
        A=D;
    end

case 2

wire [3:0] A, B, C, D;
always @(posedge CLK)
    begin
        A=D;
        C=B;
        B=A;
     end

Also.

case 3

wire [3:0] A, B, C, D;
always @(posedge CLK)
    begin
C<=B;
B<=A;
A<=D;
    end

case 4

wire [3:0] A, B, C, D;
always @(posedge CLK)
    begin
A<=D;
C<=B;
B<=A;
    end

Does anyone know how to synthesized to gate? Would you please illustrate this one?

Why don't you use any IDE (i.e. Altera Quartus II or Xilinx Vivado) to find out? — Qiu, Feb 07 '15 at 09:06
@Qiu Altera Quartus II or Xilinx Vivado are these free? and Can I know the result of synthesis to illustrate as gate? — BONGKA, Feb 07 '15 at 09:56
You can use free version of Quartus and Vivado to illustrate synthesised system. — Qiu, Feb 07 '15 at 10:52
@Qiu Thanks What is the main difference between Vivado and ISE? — BONGKA, Feb 07 '15 at 11:58
Vivado is ISE's successor, but it supports only new Xilinx fpgas (v7). — Qiu, Feb 07 '15 at 13:35

score 2 · Accepted Answer · answered Feb 07 '15 at 10:25

None of those examples should compile, The variables should be of type reg:

D Needs to be declared regarding how it is generated.

reg [3:0] A, B, C;
always @(posedge CLK) begin
  A<=D;
  C<=B;
  B<=A;
end

Here A,C and B will synthesis to flip-flops. The order of A,C and B does not matter. They describe parallel hardware.

1 Answers1