Coding an arithmetic right shift module

Question

I want to code a 16 bit Arithmetic right shift module in verilog using dataflow modeling without using bitwise operators like >>, >>> etc. Is it possible?

Answer 1

assign word_out = {  {16{word_in[31]}} , word_in[31:16]  };

This is concatenating 16 of the top bit of the word_in, with the top 16 bits of the word_in, using the replication operator {{}}.