Which of these two operations on an 8086 CPU will be faster in execution and why?

Question

The only way to know for sure is to measure it. What is your practical programming question? (Are you designing an embedded system and want to know how to lay out your data structures? In which case, don't put anything at 0x000A or 0x000B. That's the interrupt table, and the CPU uses that for other stuff.) — Raymond Chen, Jan 17 '15 at 20:02
2 could be a tiny bit faster because the address is naturally word-aligned. — 500 - Internal Server Error, Jan 17 '15 at 20:02

score 1 · Accepted Answer · answered Jan 18 '15 at 14:11

1

A transfer from memory to register on a 8086 CPU takes 8 clocks + the clocks needed to calculate the effective address.

mov ax,[0x000B]  ; Executes in 8+6+4 clocks

Aligning data on a word boundary ensures faster fetch times so one would expect that line 2 could be faster. And it is!

mov ax,[0x000A]  ; Executes in 8+6 clocks

Why do you specify the contents at those addresses? I don't expect that to influence the reading speed.

answered Jan 18 '15 at 14:11

Sep Roland

Could you explain word boundary more precisely? Unfortunately I don't understand exactly what you mean. What exactly happens in these 4 additional clocks. – JohnnyFromBF Jan 18 '15 at 15:10
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A word boundary is just saying it's a even address. The additional clocks when reading a word from an odd address stem from the fact that the CPU has to address both the word at the next lower even address and the word at the next higher even address. The CPU then uses a single byte from each to ouput a word in AX (in this case). – Sep Roland Jan 18 '15 at 15:51
It seems then that the CPU always calculates addresses with the MSb being zero. Sounds weird but fits your comment Sep. So, the contents of word at 0x0000B has to be fetched as Upper(0x0000B) ORed with Lower(0x000C)? The address bus can only address even addresses? – alvaroc Mar 17 '16 at 14:57
@alvaroc That would be *Upper(0x0000A) + 256*Lower(0x0000C)*. Memory on the 8086 is organized in 16 bit words. The address bus only deals with 2^19 addresses. All of these are *even addresses*. The CPU uses signals A0 and BHE (logically zero) to select the low byte or the high byte at an even address. (Or both signals for aligned access). So with an unaligned access 2 memory cycles are necessary which explains the additional clocks. – Sep Roland Mar 27 '16 at 13:35
Perfectly clear!. I didn´t know that all 8086 addresses are even, and yes, I forgot that 256 factor! – alvaroc Mar 28 '16 at 23:18

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