Array of interface instances of different types

Question

SystemVerilog LRM section 25.3.3 describes generic interfaces:

If a port declaration has a generic interface type, then it can be connected to an interface instance of any type.

I have an array of generic interfaces in my module:

module bing #(
    parameter     SOME_VALUE = 4
)(
    input         clk,
    interface     my_interfaces[SOME_VALUE-1:0]
);

When instantiating this module I would like to connect each interface in the array to an interface instance of a different type. Is this possible?

Alternatives / workarounds welcome - needs to be synthesisable.

score 1 · Accepted Answer · answered Jan 10 '15 at 22:34

I don't this is going to be possible to do as this would mean that in your testbench you'd have to have something like the following:

module top
  some_interface if1(...);
  some_other_interface if2(...);

  bing #(SOME_VALUE = 2) (
    .my_interfaces[0](if1),
    .my_interfaces[1](if2)
  );
endmodule

which is illegal syntax. When connecting ports, you can only use the port identifier (in your case my_interfaces) and you're not allowed to slice it (the BNF defined in 23.3.2 Module instantiation syntax doesn't allow it).

If you want to pass in an array of interfaces of the same type, then you won't have any problem. I don't think the use model you have in mind is compatible with the language. Even if when you define the my_interfaces port as an array of generic interfaces, it's still an array and it's going to expect an array of a certain type of interface to be connected to it. An array can only hold objects of the same type.

What you can do is use the maximum footprint approach and always connect all interfaces you need. You'd need to explicitly define each as an own port. Based on your parameter you'd just exclude parts of your logic (using generate statements) and the unused wires should be optimized away by your synthesis tool.

Thanks @Tudor, I suspected as much but was hoping it might be possible somehow. I sometimes think the SystemVerilog language committee was impressively short-sighted. Why can't we pass around a package or module instance as a first class object? — Chiggs, Jan 10 '15 at 23:23

score 1 · Answer 2 · answered Jan 12 '15 at 15:59

1

Your request does not make much sense. An array is, by definition, a collection of elements of identical types. No programming language that I am aware of would let the type of an element change based on the selected index.

The construct that comes closest to doing what you are looking for is a array of base class handles, with each element containing a handle to a different extension of the base class. However, if you wanted to access something that was unique to a particular extended class, you would either have to use a virtual method, or cast the element to variable of the correct type.

The problem here might not be with the language, but the fact that synthesis tools have not caught up with class based descriptions. It's a very hard problem. Even if the language let you pass around modules as objects, synthesis tools need to statically determine the type of each object.

answered Jan 12 '15 at 15:59

dave_59

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SV has defined a generic interface type, effectively to allow late-binding of a real interface. You could argue that I should be able to cast my interfaces to a generic interface type and add them to the array. It's just wiring and the types will still all be statically known at elaboration time. – Chiggs Jan 12 '15 at 16:49
I agree that the synthesis tools are way behind the curve, particularly for FPGA. However SV confused the issue since there's no definition of what should or shouldn't be synthesisable. Most synth vendors assume anything `class` related is only for verification and can therefore be ignored, with the result that [we can't even write reusable functions](http://stackoverflow.com/q/22696838/579887), in **2015?!** (VHDL could do this in **1987** I think!). That's pretty awful. – Chiggs Jan 12 '15 at 17:11
1

I propose that any program in any language that can be executed on a digital logic computer can be synthesized in digital logic hardware. It's just simple matter of space, time, and money. – dave_59 Jan 12 '15 at 17:47
@Chiggs, FYI: Verilog can create untype functions via macros w/ args (1st appeared: IEEE1364-2001 § 19.3.1, latest: [IEEE1800-2012](http://standards.ieee.org/getieee/1800/download/1800-2012.pdf) § 22.5.1). SV added the `let` construct (1st appeared: IEEE1800-2009 § 11.13, latest: [IEEE1800-2012](http://standards.ieee.org/getieee/1800/download/1800-2012.pdf) § 11.13) as a replacement; very few vendors have implanted `let`. Also, SV didn't create the synthesis confusion; it was never defined in Verilog. SV is a young standard, in time more features will become synthesizable. – Greg Jan 12 '15 at 21:19
@Greg 10 years is only young in hardware development! I think SV made the situation worse by creating an [insanely complex language](http://www.fivecomputers.com/language-specification-length.html) with far too many specific features. It's too late to simplify the language so I don't have much faith that SV will ever provide the level of (synthesisable) abstraction needed to achieve a step change in productivity. – Chiggs Jan 13 '15 at 09:34
2

To give you an idea of how slowly things move in synthesis, Synopsys added the pragmas "//translate on/off" before \`ifdef was added to Verilog in 1987. People still use these pragmas (which don't work with macros) instead of using `ifdef SYNTHESIS – dave_59 Jan 13 '15 at 17:53

Array of interface instances of different types

2 Answers2