why is there an error in end process and end architecture?

Question

i have 2 errors. the errors are in end process and end architecture. i have tried adding another end if but it is not helping.

Line 40: ERROR, syntax error near 'process'.
 Line 46: ERROR, syntax error near 'ARCHITECTURE'.

here is the full code

 LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;

ENTITY four_bit_new_counter IS
  port (clk , rst , start , stop : in std_logic ; 
        output : out std_logic_vector(3 downto 0);
        carry : out std_logic );
END ENTITY four_bit_new_counter;

ARCHITECTURE one OF four_bit_new_counter IS
signal qout: unsigned (3 downto 0);
signal cout: std_logic ;
BEGIN

    process (clk,rst,start,stop)
        begin
        if (rst ='1') then
          qout <= (qout'range => '0');
          cout <= '0' ;
      elsif (clk'event and clk = '1') then
        cout <= '0' ;
        if start='1' and stop='0' then 
                  if qout = '9' then
                    cout <= '1' ;
                    qout <= '0' ;
                  else
          qout <= qout+1 ;
        endif ; 
      end process ; 

output <= std_logic_vector(qout);
carry <= cout ;


END ARCHITECTURE one;

For one, "endif" is not valid syntax in VHDL. – fru1tbat Jan 07 '15 at 20:48 — fru1tbat, Jan 07 '15 at 20:48

score 1 · Answer 1 · 2015-01-08T03:44:30.470

There are several errors preventing your design specification from analyzing.

qout is declared unsigned (3 downto 0) and you perform an equality operation against the character literal'9'`.

You later assign qout the value of the character literal 0 instead of "0000" or x"0" or (qout'range => '0') an aggregate expression you use for resent.

The endif fru1tbat mentions should be end if.

There are two more end if statements missing see below:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity four_bit_new_counter is
    port (
        clk, rst, start,stop:   in  std_logic ; 
        output:                 out std_logic_vector(3 downto 0);
        carry:                  out std_logic
    );
end entity four_bit_new_counter;

architecture one of four_bit_new_counter is 
    signal qout: unsigned (3 downto 0);
    signal cout: std_logic ; 
begin
    process (clk,rst) -- also included ,start,stop
    begin
        if rst ='1' then
             qout <= (qout'range => '0');
             cout <= '0' ;
        elsif clk'event and clk = '1' then
            cout <= '0' ;
            if start = '1' and stop = '0' then 
                if qout = 9 then  -- was '9'
                    cout <= '1' ;
                    qout <= (qout'range => '0') ;  -- was '0'
                else
                    qout <= qout + 1 ;
                end if ;  -- was endif
            end if;       -- missing
        end if;           -- missing
    end process ; 

    output <= std_logic_vector(qout);
    carry <= cout ;

end architecture one;

And after those changes your design specification both analyzes and elaborates.

Incidentally the sensitivity list for the unlabelled process only requires rst and clk.

You can also use the IEEE package numeric_std in place of the Synopsys std_logic_arith.

The reason it complains near process and architecture are that these two reserved words are out of place inside a series of sequential statements inside an if statement because you have a series of end ifs missing closing those if statements.

why is there an error in end process and end architecture?

1 Answers1