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Is there a way in the ARM world to use only 32-bit instructions (on a Cortex M3 for example) and to disable 16-bit thumb instructions ? I'm talking about the instruction itself, not about the load/store access mechanism.

Sorry if this was already asked, or if this question is way too stupid, etc.

Thanks a lot for helping ...

yacc
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    Most Cortex-M chips only use Thumb2 mode. Really there is only *thumb* and *ARM* mode. Thumb2 is an extension of the *thumb* mode which has both 32bit and 16bit instructions and pseudo-conditional execution. All of these overloaded concepts can make this question (and answers) confusing. – artless noise Dec 23 '14 at 18:45
  • Up to Cortex-m3 there is ONLY thumb mode. M4 and M7 support Thumb2. There isn't an ARM mode on ANY Cortex-M family. – Jake 'Alquimista' LEE Dec 24 '14 at 08:41

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If you only want to force selection of 32-bit encodings over 16-bit ones where they exist, that's possible in assembly by adding the .W suffix to individual mnemonics. The assembler will then emit the 32-bit encoding or raise an error if one is not available. You thus can't simply apply it to every instruction since some only have 16-bit encodings, but knocking up some sort of grotty regex-based transformation seems feasible. If you're dealing with compiled higher-level code, then transformation of intermediate assembly listings, or hacking the assembler/compiler are probably the only viable options.

Notlikethat
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Most of the newer chips use only the Thumb-2 instruction set, which means you'll have some 16-bit instructions and some 32-bit instructions. You'll need to find older hardware if you want to use the old-fashioned 32-bit-only ARM instruction set.

Carl Norum
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  • That doesn't answer my question, mainly because I was not precise enough with my question. For what ever reasons (e.g. research) I want to disable 16-bit instructions and only run 32-bit instructions on an Cortex M3 (on my HDL model running on an FPGA for instance). Any glue how to disable 16-bit thumbs with modern compilers but continue using 32-bit thumb2 instructions (on modern chips) ? – yacc Dec 22 '14 at 19:48
  • Oh I see what you're asking. No, I don't think any compilers provide an option to do that. Assuming the 32-bit instructions are complete enough to express your whole program, you could modify clang to emit only those ones pretty easily, I'd think. – Carl Norum Dec 22 '14 at 20:32
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the cortex-m3 is only a thumb machine so it only has a 16 but thumb core, the 32 bit instructions are just undefined 16 bit extensions, so you have to use the 16 bit thumb core to even get at the 32 bit thumb2 extensions...So no by definition it is not possible.

also the 32 bit extensions are not enough to do everything you might want.

old_timer
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  • Except for the CB(N)Z instructions, I always find a 32-bit instructions “replacement” - running through the ISA quickly - , but I don't always find a 16-bit alternative. So I thought there is always most likely a 32-bit solution for a compiler and I was wondering if the optimization towards a 16-bit instruction can be discarded. This leads me to this: Can you disable individual instructions – other than using clang as suggested before? I would love to see "-disable-thumb16" or "-disable-arc-reg-t1" but I guess I have to use 16-bit instructions - I just wanted to be sure. Thank you guys. – yacc Dec 22 '14 at 21:29
  • you need to specify if you want the HARDWARE to disable these instructions or a COMPILER to not use them. the latter is possible in theory but does any compiler yet support that? not sure, is it a feature worth pursuing for them? you can certainly add it to gcc and/or llvm yourself... – old_timer Dec 22 '14 at 21:54
  • you do understand that thumb2 instruction sets vary widely between armv6m and armv7m, so this would only work on cortex-m3 and m4 but not m0, and you would have to hand check the bigger cortex-A's to see what they support – old_timer Dec 22 '14 at 21:55