Value U is missing in select

Question

Below is a few lines of code extracted from source. When I try to build the code, the "Enumerated value U is missing in select." error appears and I have no idea why. I know though, that STD_LOGIC has 9 states ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'). Dunno how to cover U.

entity cpu is
 port (  
   DATA_ADDR  : out std_logic_vector(12 downto 0);
-- a few more ports
 );
end cpu;

architecture behavioral of cpu is

   signal prog_data  : STD_LOGIC_VECTOR(12 downto 0);
   signal uk_data    : STD_LOGIC_VECTOR(12 downto 0);
   signal sel        : STD_LOGIC; 
 -- a few more signals
begin

with sel select
DATA_ADDR <= prog_data  when '0', -- error in this section
             uk_data    when '1'; 

--a few lines of code 
end behavioral;

Your 'almost-an-MCVe' is missing a context clause with package std_logic_1164 and the port declaration for `DATA_ADDR` shouldn't be followed by a `;`. — , Dec 18 '14 at 20:21

score 3 · Accepted Answer · answered Dec 18 '14 at 17:26

Two (easier) choices:

Handle it explicitly if you care about the other states (maybe for sim?):

with sel select
  DATA_ADDR <= prog_data when '0',
               uk_data   when '1',
               (others => 'X') when others;

Make an assumption if you don't:

with sel select
  DATA_ADDR <= prog_data when '0',
               uk_data   when others,

or for even easier code, use conditional assignment instead of selected assignment:

DATA_ADDR <= prog_data when sel = '0' else uk_data;

Selected assignment is akin to a sequential case statement - every possible value must be covered, and others can be used to catch the ones you don't need to handle explicitly. Conditional assignment is akin to a sequential if ... else, where you can handle whatever condition(s) you feel like - there is no requirement that you have branches for every conceivable condition.

IEEE Std 1076-2008 10.5.4 Selected signal assignments says "For a given selected signal assignment, there is an equivalent sequential statement with the same meaning." with an example case statement as an equivalent sequential statement. An if statement would be a sequential statement and legal as is. -1993 9.5.2 is more specific "The characteristics of the select expression, the waveforms, and the choices in the selected assignment statement must be such that the case statement in the equivalent process statement is a legal statement." Looks like a -1993 compliant synthesis error message. — , Dec 18 '14 at 20:32

Value U is missing in select

1 Answers1