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I'm trying to evaluate the maximum physical rate (Nyquist performance limit) of the A/Ds integrated on board various PIC microcontrollers.

However, to do the calculation requires parameters that I'm not finding explicitly stated in the datasheets, specifically Tacq, Fosc, TAD, and divisor parameters.

I've proceeded by making some assumptions but would be helpful to have a sanity check -- am I doing the maximum physical rate calculations correctly?

For illustration purposes only, I've taken the simplest possible PIC10F220 that has an ADC. This is to focus specifically on the interpretation of Tacq, Fosc, TAD, and divisor parameters, and not to suggest that any practical functionality could be implemented on this very basic chip. (This is to Clifford's points in the comments below.)

Calculation:

Nyquist Performance Analysis of PIC10F220
- Runs at clock speed of 8MHz.
- Has an instruction cycle of 0.5us  [4 clock steps per instruction]

So:

- Get Tacq = 6.06 us  [acquisition time for ADC, assuming chip temp. = 50*C]
                      [from datasheet p34]

- Set Fosc := 8MHz     [? should this be internal clock speed ?]
- Set divisor := 4     [? assuming this is 4 from 4 clock steps per CPU instruction ?]
- This gives TAD = 0.5us          [TAD = 1/(Fosc/divisor) ]
- Get conversion time is 13*TAD   [from datasheet p31]
- This gives conversion time 6.5 us
- So ADC duration is 12.56 us   [? Tacq + 13*TAD]

Assuming 10 instructions for a simple load/store/threshold done in real-time before the next sample (this is just a stub -- the point is the rest of the calculation):

- This adds another 5 us   [0.5 us per instruction]
- To give total ADC and handling time of 17.56 us    [ 12.56us + 1us + 4us ]
- before the sampling loop repeats  [? Again Tacq ? + 13*TAD + handling ]

- If this is correct, then the max sampling rate is 56.9 ksps   [ 1/ total time ]
- So the Nyquist frequency for this sampling rate is 28 kHz.    [1/2 sampling rate]

Which means the (theoretical) performance of this system --- chip's A/D with the hypothetical real-time handling code --- is for signals that are bandlimited to 28 kHz.

Is this a correct assignment / interpretation of the data sheet in obtaining Tacq, Fosc, TAD, and divisor parameters and using them to obtain the maximum physical rate, or Nyquist performance limit, of this chip?

Thanks,

Assad Ebrahim
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    Given the parts tiny memory (16bytes of SRAM), and limited I/O (it only has 6 pins in total, with just three of them digital output capable) what are you going to do with these samples once you have them? You cannot store the samples and you cannot output them to some other device faster than you can capture them (because bit-banging is your only option). It is quite apparent to me that these devices are not intended for an application requiring this kind of performance. What are your actual performance and application requirements and budget? – Clifford May 01 '10 at 08:47
  • "This would be preferable to using external A/D chips.": External to what I wonder? Couldn't that part have an ADC built-in? The part you have suggested is already less capable than most SPI or I2C ADC devices. – Clifford May 01 '10 at 08:59
  • @Clifford: The PIC10F220 in the example above was selected ONLY to walk through the simple example to check that I'm interpreting Tacq, Fosc, TAD, and divisor correctly in working through this sort of Nyquist analysis. The actual chips I'm considering for the design are the dsPIC33FJ128MC804 (with 16b A/D) or dsPIC30F3014 (with 12b A/D). Re: "preferable to using external A/D chips" -- by this I meant the PIC option is appealing because if it is suitable it would mean doing away with dedicated A/D chips and a separated dedicated DSP, with all the support chips such a design takes. – Assad Ebrahim May 01 '10 at 09:32

2 Answers2

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You're not going to be able to do much processing in 8 instructions, but assuming you're just doing something simple like storing the incoming samples to a buffer, or detecting a threshold, then your analysis looks good.

Paul R
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  • The device has just 16 bytes of SRAM - not much buffering! It also has limited I/O; bit-banging the data out will require a *minimum* of 8 instruction cycles. – Clifford May 01 '10 at 08:50
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The actual chips I'm considering for the design are the dsPIC33FJ128MC804 (with 16b A/D) or dsPIC30F3014 (with 12b A/D).

That is an important distinction; the dsPIC ADC supports ping-pong DMA transfers of multiple channels simultaneously, so can minimise the effective software overhead per sample. That makes the calculation a somewhat different one. You need to determine from the sample rate and the DMA buffer size the time between sample buffer interrupts; that is how much processing time you have to deal with each buffer. If you are using Microchip's DSP library, it gives precise cycle time formulae for each algorithm, and block processing is considerably more efficient that sample-by-sample processing.

My last project was on a dsPIC33 with two channels sampled at 48KHz and 32word sample buffers (giving 667us to process each pair of buffers). The software processing was therefore entirely independent of the sampling since by using DMA they take place simultaneously.

Clifford
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  • (+1) Appreciate the detailed hardware specific answer. Was however, hoping that someone would go through the calculation steps and validate/spot flaws in the assumptions I've used. My interest is independent of the hardware -- it is about whether I can indeed conclude that the **theoretical** max performance of the A/D is a 28kHz bandlimited signal. – Assad Ebrahim Aug 18 '12 at 22:49
  • Different processors work in different ways so the calculation will be different each time - refer to the data sheet. The point was if you have software overhead in your sampling, interrupts or non-deterministic control flow for example, will cause your sampling to be aperiodic. This can be disastrous for signal fidelity. If you are trying to sample at the highest possible rate then this effect will be significant. DMA buffering is a solution to that problem, and should be used when high sample rates are required relative to the processor clock rate. – Clifford Aug 26 '12 at 08:24
  • Ok, I see. Fair point. But then how would you determine the performance envelope of a given A/D -- how would you approximate the upper bandwidth that it can handle, taking into account your point about software overhead? – Assad Ebrahim Aug 26 '12 at 08:29
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    @AKE: The maximum physical rate is determined by the hardware and clocking as you have calculated. If this is free-running rather than software triggered the rate will be exactly periodic, however if you have to perform processing on each sample that processing must complete within the sample time otherwise you won't keep up, and unprocessed samples will be overwritten. If you software trigger the sampling, you won't miss a sample but they may be aperiodic or of non-deterministic or non-specific frequency. – Clifford Aug 26 '12 at 20:30
  • @AKE: If you don't have DMA, then you might trigger sampling from a timer, then use the conversion complete interrupt, the handler of which simply copies the sample to a buffer, then you perform processing when the buffer is full, at the same time switching to a second buffer to be filled while processing the first. The software overhead in processing a buffer of samples is likely to be lass that processing each sample, so a higher rate can be maintained. – Clifford Aug 26 '12 at 20:34
  • Thanks for elaborating, yes, makes sense for software triggered sample. Will keep the two modes in mind. Appreciate your returning to the thread. I will edit my original question to reflect the terminology 'maximum physical rate'. Cheers. – Assad Ebrahim Aug 26 '12 at 22:21