Verilog code to count Number Repetition

Question

I'm writing verilog code for an algorithm,but I have a problem with one module that receives for example:10 binary numbers (4 bits for each one)from previous module (1 input at every positive edge clk) so there are 10 clock cycles to have the 10 binary numbers.

How to Calculate the number of times each number repeats and save the frequency for each number for later use by another module using verilog hardawre language? for example : at the end this module find 0000 twice ,0001 once,....,1111 zero. at the 10 clock cycles.

Thanks in advance...

I have tried "generte counters for each one " but it didn't work. I give example above but my work depends on random numbers generated at every positive edge clk then I want to count how many every numbers at the range[0000,1111]appears during 10 clk cycles . — Sereena, Dec 04 '14 at 22:05
The simplest way I can see, is declaring an array of 16 elements, which will serve as counters, and increase them each time the number corresponding to the counter's index is occurring. But once again, what kind of output format do you want to get? — Eugene Sh., Dec 04 '14 at 22:29
Can you write what you said as verilog code ?I am beginner with verilog. the output will be freq for each number that will be added with another value calculated by another module ,but until now I didn't know how to do that :( — Sereena, Dec 04 '14 at 22:36
Ok now I used array it's more simple :) but if I want to initializing array (with large size)to value "zero" how can I do that without using for loop?because I want to write synthesis code — Sereena, Dec 05 '14 at 01:19
You should have a reset input into your module, which is triggering all of the initialization stuff you might want. — Eugene Sh., Dec 05 '14 at 15:20
It's agood answer Morgan thank you very much,but now I am trying to write it as synthesis code "without for loop".. — Sereena, Dec 10 '14 at 01:06
@Sereena my answer is fully synthesisable. The for loop can be unrolled at compile time so is no issues for synthesis. It is based on parameters or static values (16) then it is no different to manually writing it out. — Morgan, Dec 10 '14 at 07:47
Yes I do it and it's work thank you Morgan , but I have now only one problem in below code : genvar i; generate for (i=0;i<4;i=i+1) begin Test m(in,out); end endgenerate There is one error when synthesize my code "Block identifier is required on this block" How can I solve this warning??is there any problem with the syntax? Thank you in advance... — Sereena, Dec 11 '14 at 03:19

score 0 · Accepted Answer · answered Dec 05 '14 at 11:29

Assuming you have a clock and active low reset:

module tracker(
  input clk,
  input rst_n,
  input [3:0] data_rx
);

reg  [7:0] count [0:15];
integer i;

always @(posedge clk, negedge rst_n) begin
  if (~rst_n) begin
    for(i=0; i<16, i=i+1) begin
       count[i] <= 8'b0;
    end
  end
  else begin
    count[data_rx] <= count[data_rx] + 1;
  end
end
endmodule

For an FPGA defaults an initial block can be used instead of the reset signal that could look like:

initial begin
  for(i=0; i<16, i=i+1) begin
     count[i] <= 8'b0;
  end
end

always @(posedge clk) begin
  count[data_rx] <= count[data_rx] + 1;
end

Note that a for loop has been used in the asynchronous reset and initial, This can be statically unrolled, there is no dynamic target so is fully synthesizable.

Verilog code to count Number Repetition

1 Answers1