I want to ask about switching one bit for example x[3] in bit vector x[0:3] to one if it's zero or to zero if it's one in verilog.So if x=0101 it will become x=0100 .I have tried concatination with not but it's error in verilog .Can you help me to do that? My code is here :http://www.edaplayground.com/x/JAc where x:input and y:x after mutate one bit
Thanks in advance.