Verilog Return X for Every Test Case In Generate Syntax for Barrel Shifter

Question

In Wrote A module for 8 bit barrel shifter and rotate, and it return x for outputs, i don't know how to solve it ! I should write this module with generate syntax, i uploaded picture for 4 bit barrel shifter and rotate

modeling

module OneGate(input D, S, W0, output W);
    wire Temp;
    and (Temp, D, S);
    or (W, Temp, W0);
endmodule

module Barrel_Shifter_8_bit(input [7:0]D, [7:0]S, SbarR, output [8:0]W);
    integer i;
    wire Temp;
    wire [8:0]WW[8:0];
    genvar col, row;
    generate
        for (row = 0; row < 8; row = row + 1) begin
            for (col = 0; col < 8; col = col + 1) begin
                if (col == 0) begin
                    assign WW[row][0] = 0;
                end
                if (row + col < 8)
                    OneGate Gates(D[row + col], S[col], WW[row][col], WW[row][col+1]);
                else
                    OneGate Gates(D[col - ( 3 - row)] & SbarR, S[col], WW[row][col], WW[row][col+1]);
            end
        end
    endgenerate
    assign W = '{WW[0][7], WW[1][7], WW[2][7], WW[3][7], WW[4][7], WW[5][7], WW[6][7], WW[7][7], WW[8][7]};
endmodule

module Test;
    reg [7:0]In = '{0, 0, 1, 1, 0, 0, 0, 0};
    reg [7:0]Se = '{0, 0, 0, 0, 0, 0, 1, 0};
    wire [8:0]W = '{0, 0, 0, 0, 0, 0, 0, 0, 0};
    Barrel_Shifter_8_bit TempB(In, Se, 0, W);
    initial begin
        #10;
        #50 Se = '{0, 0, 0, 0, 1, 0, 0, 0};
        #50 Se = '{0, 0, 0, 0, 0, 1, 0, 0};
        #50 Se = '{0, 0, 0, 0, 0, 0, 0, 1};
        #50 Se = '{0, 0, 0, 0, 0, 0, 1, 0};
        #50;
    end
endmodule

score 1 · Accepted Answer · answered Nov 11 '14 at 23:51

you have multiple drivers on W in your testbench. Change wire [8:0]W = '{0, 0, 0, 0, 0, 0, 0, 0, 0}; to wire [8:0] W; and you will see 1s where there where Xs.

Other notes:

'{} as assigning a packed array is very uncommon. I recommend changes to a more standard format. Example: Se = '{0, 0, 0, 0, 1, 0, 0, 0}; to Se = 8'b0000_1000; or Se = 8'h8;
input [7:0]D, [7:0]S, SbarR, output [8:0]W infers SbarR as [7:0] SbarR. Recommend changing to input [7:0] D, S, input SbarR, output [7:0] W
W[8], WW[8], and WW[*][8] are never used, make them 8-bit wide instead of 9-bits. wire [7:0] W;, wire [7:0] WW [7:0];

Verilog Return X for Every Test Case In Generate Syntax for Barrel Shifter

1 Answers1