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A (hopefully) simple question.

Can I create my MMU page tables in ARM tightly coupled memory, or is there a restriction that prevents me doing this.

I have 16k of data TCM that seems quite suitable for this task (the instruction TCM will contain my secure world code), but I'm getting abort exceptions when enabling the MMU.

When I compile my secure world code to target SRAM everything works as expected. The problem is that on this SoC SRAM is available from an FPGA-like device that does not respect TrustZone at all.

Am I missing something here, or do I need to carve off a small piece of RAM for myself to get this all working?

I'm working on an ARM1176JZ-S.

Michael van der Westhuizen
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1 Answers1

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So, many years later I found my answer in the ARM Architecture Reference Manual for ARMv6 while browsing around for something completely different!

In section B4.7.3, Page table translation in VMSAv6 (page B4-25), the answer is mentioned just after discussing whether L1 cache is used in the page table walk, and it says:

Hardware page table walks cannot cause reads from TCM.
Michael van der Westhuizen
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