0

I'm designing a MIPS based processor and I am tasked with creating an instruction memory and data memory with the below memory mapped.

Your instruction memory should be implemented with an “altsyncram” component, a 32-bit output bus, an 8-bit address bus, a 256 word capacity, and mapped to the memory block beginning at address 0x00400000.

Your data memory should be implemented with an “altsyncram” component, a 32-bit input/output bus, an 8-bit address bus, a 256 word capacity, and mapped to the memory block beginning at address 0x10000000. Your data memory should also have ram enable, write enable, and byte enable signals.

However, I am not sure how to implement this in VHDL.

Aort49
  • 13
  • 1
  • 3
  • Homework? If you truly want to learn how to design a CPU, including memory mapped memory, you may want to look at some of the good references in this prior answer to [Project on MIPS pipelined processor](http://stackoverflow.com/a/17617679/2352082). – Morten Zilmer Oct 22 '14 at 16:39
  • 1
    Your assignment is for a single cycle implementation. Morten's reference is for doing a pipelined version, a natural progression in a course of study. There is a single cycle implementation described and shown in the 32-bit MIPS VHDL model varying in subtle ways from your current assignment (the course text is very particular). Note the bit in the EEL-4713C [Class Policies](http://www.ann.ece.ufl.edu/courses/eel4713_14fal/eel4713_policies.pdf) on academic honesty, it colors responses here. Ask specific questions, and this isn't the place to learn VHDL. –  Oct 22 '14 at 19:01

1 Answers1

0

altsyncram is a megafunction available in Altera. You need to first create it in the Quartus II software under a project.

your question is too large of a scope to answer in one post.

There are multiple parts to a mips microprocessor. A general RISC microprocessor are designed in 4 stage pipelines

1)Fetch instruction: Here Instructions are loaded from program memory and pushed into the pipeline

2)Decode Instruction: Here the information that was pushed from 1) is decoded here. For example if the instruction is $1 add $2 (register 1 plus register 2) then it will be pushed into the pipeline for processing

3)Execute Instruction: Here the information is executed via a ALU. It can be arithmetic operation, branch compare, etc etc

4)Memory writeback: Information is written back into the data memory where information is stored if the information is not being used in the general register set.

Your question is prompting either the design of the Instruction Fetch stage or the Memory writeback stage. If you are not familiar with VHDL, then you should learn it first.

If you are attempting to learn VHDL while learning Computer Architecture design, then I think you are in the wrong place, because it can be one of the toughest courses you may ever encounter in your university. You may try looking at Schematic design using BDF instead.

CJC
  • 795
  • 8
  • 25