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I am going through a data-sheet and read "Single-cycle multiplication and hardware division" as part of STM32 specifications, i am not sure i understand what that means. From what I read on the Net, multiplication is usually easier to compute than division. Would that mean that STM's can compute both multiplication and division within one cycle?

Please assist.

the swine
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dede9714
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  • binary multiplication is just shifting and adding and was traditionally broken into multiple clock cycles, but you can reduce the clock cycles down to as little as one by consuming (relatively) vast quantities of logic, and that is becoming more normal if you have a multiply at all in your instruction set. – old_timer Oct 16 '14 at 14:43
  • having a divide in your instruction set is not typical but if you do it is normally an iterative process meaning takes multiple steps meaning takes more than one clock. I assume one could argue with enough logic and a long enough clock it could be done, I would be surprised to see one esp in an stm32, I am also surprised to see a single cycle multiply – old_timer Oct 16 '14 at 14:46

1 Answers1

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When it comes to the multiplier, it means that it takes only one clock cycle (this is, for 100Mhz, 10 nanoseconds) to perform the operation.

However, the division is usually performed in an iterative fashion, bit by bit, and the particular implementation (the core instruction set) should be looked into.

Having a look at Cortex M-Series you see that the multiplication is in fact single-cycle, however the division lasts 2-12 cycles, and in the footnote regarding this:

Division operations use early termination to minimize the number of cycles required based on the number of leading ones and zeroes in the input operands.

Added:

Notice, however, that the only INTxINT multiplications are single-cycle, whereas LONGxLONG last 3-5 cycles (as a LONGxLONG mult can be performed as a combination of INTxINT multiplications and additions)

Manex
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    Perhaps "clever" wording: *"Single-cycle multiplication and hardware division"*, does not actually say the divide is single cycle - only that it is performed in hardware. – Clifford Oct 17 '14 at 07:38
  • True, and if the F4 is the MCU the OP is considering then that's also the case for the hardware FPU. `vmul.f32` is 1-cycle whereas `vdiv.f32` is 14-cycles. – Andy Brown Oct 17 '14 at 08:36
  • @panto111088 If this answered your question please accept it. – Jonathan Mee May 17 '16 at 18:07