how to define N bus with width 32bit

Question

I wanted to define large number of bus with bus width 32bit.

for example

input [31:0] a0, a1, a2, .... aN;
input [31:0] b0, b1, b2, .... bN;
output [31:0] c0, c1, c2, .... cN;

c0 = a0 + b0;
c1 = a1 + b1;
.
.
cN = aN + bN;

how can I realize this code with iteration?

How about using arrays and flatten them? http://stackoverflow.com/questions/16369698/how-to-pass-array-structure-between-two-verilog-modules — Chubosaurus Software, Oct 11 '14 at 02:01

Morgan · Accepted Answer · 2014-10-11T04:20:59.450

Verilog Generates are designed for solving this issue. It would be easier if you can use unpacked arrays for ports.

Statements need to be contained in an initial or always, to imply the output is a flip-flop use always @(posedge clk) for a combinatorial circuit use always @*.

module example (
  parameter N = 10
)(
input             clk,
input      [31:0] a [0:N],
input      [31:0] b [0:N],
output reg [31:0] c [0:N]
);

genvar i;
generate
for(i=0; i<=N; i++) begin
  always @(posedge clk) begin
      c[i] <= a[i] + b[i];
  end
end
endgenerate

endmodule

Generates are good when you need to parameterise module instance, the above can be rewritten with a plain for loop.

integer i;

always @(posedge clk) begin
  for(i=0; i<=N; i++) begin
    c[i] <= a[i] + b[i];
  end
end

For synthesizable code the for loop must be able to be statically unrolled.

how to define N bus with width 32bit

1 Answers1