Text output file not instantiated

Question

I have two newbie questions. I am attempting to output the data from an array into a text file on vhdl. Despite referencing many online guides to do this, I always come up with a "file does not exist". Any suggestions on what's going wrong?

Secondly, when I try to use the array signal below as an argument to the write function, it gives an error. How else can I use non-constant data as an operand?

entity Top_Module is
Port ( clk : in  STD_LOGIC);
end Top_Module;

architecture Behavioral of Top_Module is

type array_1 is array (0 to 127) of integer range -128 to 127;
signal sample_1: array_1  := (104,40,-40,-104,-128,-104,-40,40,104,127,104,40,40,-4);
constant  a :std_logic_vector(3 downto 0):= "0111";
begin


process(clk)    -- process for writing the outputs to the "*.txt" file
file result_file: text  is out "fft_output.txt";
variable outline:line;
constant tmp_fft:integer:=0;
begin
    if(clk'event and clk='1') then
                --tmp_fft  :=to_integer(signed(sample_1));
                write(outline,a);
                writeline(result_file,outline);
    end if;
end process;

Answer 1

The file declaration is VHDL 1987 syntax, so try with this instead:

file result_file : text open write_mode is "fft_output.txt";

Your code does not show it, but I assume you include the std.textio package like:

library std;
use std.textio.all;

In VHDL 2002, this package does not know how to make (write) a line from std_logic_vector as attempted in write(outline, a). So if you are using VHDL 2002, the problem may be due to lacing support for std_logic_vector arguments in the write procedure.

The non-standard Synopsys package std_logic_textio is available in most tools, and includes a write function for std_logic_vector. This package can be used with:

library ieee;
use ieee.std_logic_textio.all;

VHDL 2008 standard added support for write of std_logic_vector in the std_logic_1164 package, so you may want to check if the simulator you are using has support for this feature in VHDL 2008. Note that binary and hex output is also supported with bwrite and hwrite.

Note that synthesis using write and in general textio is not possible, since these are based on the line type, which again is an access type, similar to pointer types in other languages, and this can't be synthesized. For synthesis use a function the the slv_image in David Koontz's answer.

Answer 2

In addition to Morten's answer you also didn't represent every element of sample_1 in the aggregate default value, which can be cured by appending , others => 0 before the closing parenthesis.

Because your VHDL design specification was otherwise IEEE Std 1076-1987 compliant I genned a bit together using ghdl's --std=87 flag using a string conversion routine I had sitting around. (And the lack of 'VALUE in -1987 was a bother):

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity Top_Module is
Port ( clk : in  std_logic);
end Top_Module;

architecture Behavioral of Top_Module is
    function slv_image(constant inp: std_logic_vector) return string is
        variable image_str: string (1 to inp'length);
        alias input_str:  std_logic_vector (1 to inp'length) is inp;
    begin
        for i in input_str'range loop
            case input_str(i) is
                when 'U' => image_str(i) := 'U';
                when 'X' => image_str(i) := 'X';
                when '0' => image_str(i) := '0';
                when '1' => image_str(i) := '1';
                when 'Z' => image_str(i) := 'Z';
                when 'H' => image_str(i) := 'H';
                when 'L' => image_str(i) := 'L';
                when 'W' => image_str(i) := 'W';
                when '-' => image_str(i) := '-';
            -- image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
            end case;
        end loop;
        return image_str;
    end;
    type array_1 is array (0 to 127) of integer range -128 to 127;
    signal sample_1: array_1  := (104,40,-40,-104,-128,-104,-40,40,104,127,104,40,40,-4, others => 0);
    constant  a : std_logic_vector(3 downto 0):= "0111";
begin

Unlabelled:
    process(clk)    -- process for writing the outputs to the "*.txt" file
        file result_file: text  is out "fft_output.txt";
        -- file result_file : text open write_mode is "fft_output.txt";
        variable outline: line;
        constant tmp_fft:integer := 0;
    begin
        if(clk'event and clk='1') then
                    --tmp_fft  :=to_integer(signed(sample_1));
                    write(outline,slv_image(a));
                    writeline(result_file,outline);
        end if;
    end process;
end Behavioral; -- architecture;

With a test bench:

library ieee;
use ieee.std_logic_1164.all;

entity tb_topmod is
end tb_topmod;

architecture foo of tb_topmod is
    signal clk:  std_logic := '0';
    component Top_Module   -- no is
        Port ( clk : in  std_logic);
    end component;
    for DUT: Top_Module use entity work.Top_Module(Behavioral);
begin
DUT:
    Top_Module   -- entity work.Top_Module
        port map (clk => clk);
CLOCK:
    process
    begin
        wait for 20 ns;
        clk <= not clk;
        if Now > 100 ns then
            wait;
        end if;
    end process;
end foo;

ghdl -a --std=87 topmod.vhdl
ghdl -e --std=87 tb_topmod foo
ghdl -r tb_topmod foo

(Which analyzes, elaborates and runs (simulates) the design.)

The file fft_output.txt file contains:

more fft*
0111
0111
0111

Which is the expected output with the Now test in the test bench's CLOCK process. Your design specification only supplies a default value for a.

Now are you really using a VHDL -1987 tool?