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I need pseudo random numbers generated for hardware (either in VHDL or Verilog) that meet the following criteria.
- Each number is 1-bit (doesn't have to be, but that would complicate things more) - The N pseudo random numbers cannot be correlated with each other. - The N pseudo random numbers need to be generated at the same time (every clock edge).

I understand that the following will not work : - Using N different seeds for a given polynomial - they will simply be shifted versions of each other - Using N different polynomials for a given length LFSR - not practical since N can be as large as 64, and I don't know what length LSFR would give 64 different tap combinations, too huge if possible at all.

If using LFSR, the lengths do not need to be identical. For a small N, say 4, I thought about using 4 different prime number lengths (to minimize repeatability), e.g., 15, 17, 19, 23, but again, for a large N, it gets very messy. Let's say, something on the order of 2^16 gives sufficient length for an LFSR.

Is there an elegant way of handling this problem? By elegant, I mean not having to code N different unique modules (15, 17, 19, 23 above as an example). Using N different instances of Mersenne Twister, with different seeds? I do not have unlimited amount of hardware resources (FF, LUT, BRAM), but for the sake of this discussion it's probably best to ignore resource issues.

Than you in advance.

mxo
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  • This does not feel like a programming question but more of a mathematical one. – Morgan Sep 23 '14 at 07:04
  • '15, 17, 19, 23, but again, for a large N, it gets very messy. Let's say, something on the order of 2^16 gives sufficient length for an LFSR.' 15, 17 etc are your fft length, what does 2^16 refer to? – Morgan Sep 23 '14 at 07:05
  • Yes, it can definitely be seen as a mathematical question. I've just been engrossed in HDL design, so was looking for a way to somehow easily implement without getting so deep in math... – mxo Sep 24 '14 at 03:07
  • 15, 17, 19, 23 are the length in LFSR, number of shift registers, resulting in 2^15-1, 2^17-1, 2^19-1, 2^19-1 would be the respective period of those LFSRs. 2^16 (minus 1) is referring to a 16 length LFSR, on the order similar to 15, 17, 19, 23. Sorry I wasn't clear. – mxo Sep 24 '14 at 03:08
  • Perhaps I should start a different thread, not making it a HDL question... – mxo Sep 24 '14 at 03:28
  • Sorry I was not clear in my suggestion, I actually think you might get a better response from [MathSE](http://math.stackexchange.com/) or [DSP-SE](http://dsp.stackexchange.com/). I do understand the interest to think about implementation at this level but it might be best to separate the approach from implementation. I do not post to those other Stack Exchange sites so they might say it is off topic for them, but good luck. – Morgan Sep 24 '14 at 07:02

1 Answers1

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One option is to use a cryptographic hash, these are typically wide (64-256 bits), and good hashes have the property that a single bit input change will propagate to all output bits in unpredictable fashion. Run an incrementing counter into the hash and start the counter at a random value.

The GHASH used in AES-GCM is hardware-friendly and can generate new output values every clock.

Guy
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