The speed ratings you are talking about - 50 MHz, 100 MHz, 2 MHz - are basically slew rates controlling how fast the I/O pin changes state.
This has essentially nothing to do with the programming of the counters/timers used to actually generate the signal - it should not be confused with a clock prescaler
which reduces the clock rate going into the timer, potentially drastically reducing the power consumption (most power in CMOS circuits is used charging and discharging implicit capacitance when changing state) but also the timing resolution.
In contrast, the slew rate reduction is something like a crude low-pass filter on the output. It does potentially mean less power consumed driving the output (or at least the power spread over a greater amount of time), but most of the power consumed by a counter/timer will be in clocking the counter itself.
If your output frequency is well below the slew rate limit, and your external circuit can tolerate slow transitions you could try setting this.
Of course if your output frequency approaches the slew rate limit, you may find that your signal fails to drive all the way to valid logic levels.