SystemC: channels vs port value update

Question

While working on a SystemC project, I discovered that probably I have some confused ideas about signals and ports. Let's say I have something like this:

//cell.hpp

SC_MODULE(Cell)
{ 
   sc_in<sc_uint<16> > datain; 
   sc_in<sc_uint<1> > addr_en;
   sc_in<sc_uint<1> >  enable;
   sc_out<sc_uint<16> > dataout;

   SC_CTOR(Cell)
   {
     SC_THREAD(memory_cell);
        sensitive << enable << datain << addr_en;
   }
   private:
   void memory_cell();
};



//cell.cpp

void Cell::memory_cell()
{  
   unsigned short data_cell=11;

   while(true)
   {     
      //wait for some input
      wait();     

      if (enable->read()==1 && addr_en->read()==1)
      {        
         data_cell=datain->read();        
      }

      else
      {
         if(enable->read()==0 && addr_en->read()==1)
         {
            dataout->write(data_cell);
         }
     }
   }
}





//test.cpp

SC_MODULE(TestBench)
{
   sc_signal<sc_uint<1> > address_en_s;
   sc_signal<sc_uint<16> > datain_s;  
   sc_signal<sc_uint<1> >  enable_s;
   sc_signal<sc_uint<16> > dataout_s;   

   Cell cella;

   SC_CTOR(TestBench) : cella("cella")
   {
        // Binding
        cella.addr_en(address_en_s);
        cella.datain(datain_s);
        cella.enable(enable_s);
        cella.dataout(dataout_s);               
        SC_THREAD(stimulus_thread);                        
   }


  private:
    void stimulus_thread() {  

//write a value:    
        datain_s.write(81);    
        address_en_s.write(1);    
        enable_s.write(1);         
        wait(SC_ZERO_TIME);


//read what we have written:
        enable_s.write(0);
        address_en_s.write(1);
        wait(SC_ZERO_TIME);

        cout << "Output value: " << dataout_s.read() << endl;


//let's cycle the memory again:       
        address_en_s.write(0);         
        wait(SC_ZERO_TIME);
        cout << "Output value: " << dataout_s.read() << endl;

    }   
};

I've tried running this modules and I've noticed something weird (at least, weird for me): when the stimulus writes a value (81), after the wait(SC_ZERO_TIME) the memory thread finds its datain, enable and address_enable values already updated. This is what I expected to happen. The same happens when the stimulus changes the enable_es value, in order to run another cycle in the memory thread and copy the data_cell value into the memory cell dataout port. What I don't understand is why after the memory module writes into its dataout port and goes again to the wait() statement at the beginning of the while loop, the stimulus module still has the old value on its dataout_s channel (0), and not the new value(81), which has just been copied by the memory module. Then, if I run another cycle of the memory loop (for example changing some values on the stimulus channels), the dataout channel finnally updates.

In other words, it looks like that if I write into the stimulus channels and then switch to the memory thread, the memory finds the values updated. But if the memory thread writes into its ports, and then I switch to the stimulus thread, the thread still sees the old values on its channels (binded to the memory ports).

score 0 · Answer 1 · edited Apr 15 '18 at 19:27

The example above is not working as I expected because of a wrong delta cycle synchronization.

Generally speaking, lets suppose we have two threads running on two modules, A and B, connected through a channel. If I write something in threadA during delta cycle number 1, it will only be available in thread B during delta cycle 2. And if thread B writes something during its delta cycle 2, thread A has to wait until delta cycle 3 in order to read it.

Being aware of this, stimulus thread would need two consecutive wait(SC_ZERO_TIME) statements in order to read the correct output from the memory, because it has to forward its delta value.

SystemC: channels vs port value update

1 Answers1