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I would prefer to avoid a recursive call of make. Unless someone recommends this, it seems inefficient. (if someone does recommend it, we can mark as duplicate of How can I call a specific target from my makefile?)

I've found related threads but most of the solutions involve refactoring the make command, e.g. makefile execute another target

or depending on the target that you want to run, e.g. How do I make a target in a makefile invoke another target in the makefile

In fact, I would be interested in how to refactor my makefile. I am newbie with makefiles so I wouldn't be surprised if I'm making things more complicated than they need to be.

# depend on all files in folder abc
myTarget1: $(shell find abc -type f)
  make otherTarget
  some commands...

# I have various targets that need to do the following:
.PHONY : otherTarget
otherTarget:
  common commands...
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  • You have a number of make targets which all have the same shell commands that need to be run as part of their body? – Etan Reisner Jul 31 '14 at 02:03
  • @EtanReisner yes. I also run the target by itself. – Xu Wang Jul 31 '14 at 02:39
  • That sounds like something that should be in a shell script that you can then call from the various targets and have a target to call manually to me. Barring that then a make `define` sounds like what you want. – Etan Reisner Jul 31 '14 at 02:44
  • @EtanReisner Thank you Etan, I will think about this possibilities. – Xu Wang Jul 31 '14 at 03:17
  • The direct answer to the question is no, there is no way to invoke a specific target from within the recipe of another target except by invoking make recursively. – MadScientist Aug 08 '14 at 13:33

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