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This is an ARM errata for Cortex A9 processors.

Description:-

An imprecise external abort received while the processor is ready to enter into WFI state might cause a processor deadlock. Explicit memory transactions can be completed by inserting a DSB before the WFI instruction. However, this does not prevent memory accesses generated by previously issued PLD instructions page table walks associated with previously issued PLD instructions or as a result of the PLE engine. If an external abort is returned as a result of one of these memory accesses after executing a WFI instruction, the processor can cause a deadlock.

So, how to prevent the deadlock by protecting the MMU.

user1768114
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  • Sounds like you shouldn't perform the WFI directly after a PLD. But you probably should explain a LOT more about your situation. Are you writing an OS or a user-mode program, to name just the first on many details we'll need. – MSalters Jul 18 '14 at 07:31
  • **Source : Cortex-A9 Technical reference Manual(ARM)** The micro TLB returns the physical address to the cache for the address comparison, and also checks the protection attributes to signal either a Prefetch Abort or a Data Abort. So,could you please help me how to disable the prefetch/data abort signalling by writing to coprocessor(cp15) using **MCR Instruction **@Brendan – user1768114 Jul 22 '14 at 04:20

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