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I am new to MSP430 architecture and I am porting an RTOS which is written for ARM Cortex M3 into this architecure. In ARM Cortex architecture, there are PSP and MSP registers to hold stack values for execution modes.

As I understand from MSP430 architecture there is only just one stack pointer register (SP).

Here are my questions:

-Is there only one register bank for SP within interrupt/execution context?

-Can I use regular C functions for interrupt handling in MSP430 as in ARM Cortex?

-How does MSP430 handle (save/restore) registers during interrupt execution (specifically SP, SR and PC)?

albin
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1 Answers1

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  1. There are no banks in terms of MSP430 registers, it is the only one SP register within context. enter image description here

  2. Yes, you can use C functions for interrupt handling link

__interrupt void MyFuncISR(void)

or it also can be like

#pragma vector=TIMER0_A0_VECTOR    
__interrupt void
ta0cc0_isr (void)

in this case compiler will set the proper interrupt vector by the define/name you provide

3. The interrupt logic executes the following: 1. Any currently executing instruction is completed. 2. The PC, which points to the next instruction, is pushed onto the stack. 3. The SR is pushed onto the stack and so on, see below: enter image description here

Ruslan Gerasimov
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  • (answer 2) MSP430 architecture does not support C functions as interrupt handlers. Therefore you are using '__interrupt' specifier to change calling convention. Within interrupt context you should return from handler via 'reti' in order to pop sr from the stack. On the other hand in regular C call you should use 'ret' instructions. – albin Jun 25 '14 at 17:24
  • The compiler puts `reti` in the return of interrupt C call with the specifier `__interrupt` automatically, doesn't it? That's why `__interrupt` specifier offered. – Ruslan Gerasimov Jun 25 '14 at 23:31
  • Problem starts at this point, if you want to context switch within an ISR (e.g.: timer interrupt) you should also consider not to save/restore SR. This is handled by hardware. In contrast you should should save/restore SR in regular execution. Briefly you cannot use uniform save/restore scheme for both execution and ISR context. In ARM Cortex M, interrupt controller comply with AAPCS (ARM Application Procedure Call Standard), therefore, you may use regular C functions(without using special specifiers e.g.: __interrupt, __irq, __attribute__((interrupt(irq))), etc.) as interrupt handlers. – albin Jun 26 '14 at 17:10