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I am trying to make a BCD converter to show numbers from 0 to 9999, I need to implement Double Dabble Algorithm using the shift operators. But I just cannot start coding without running into warnings i dont really know about, I am still a beginner so please ignore any stupid mistakes that I make. I started off by first implementing the algorithm. I have never used shift operators so I am probably not doing it right, please help, here is my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity algorithm is
Port (x: in unsigned (15 downto 0);
        y: out unsigned (15 downto 0));
end algorithm;

architecture Behavioral of algorithm is

    begin
    y <= x sll 16;

end Behavioral;

And the error

Xst:647 - Input <x> is never used. This port will be preserved and left unconnected 
if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of 
this sub-block is preserved.

Even if I implement this

y <= x sll 1;

I get this error

Xst:647 - Input <x<15>> is never used. This port will be preserved and left 
unconnected if it belongs to a top-level block or it belongs to a sub-block 
and the hierarchy of this sub-block is preserved.

What am I doing wrong here?

alexhilton
  • 125
  • 8
  • Double dabble implies a bcd accumulator, cleared so the dabble works. There's a binary value that is left shifted into the bcd accumulator bit at a time. First you shift the bcd accumulator left one position, then you set the right most position to the value found in the left most position of the binary value, then you shift the binary value left one position. Then for each of the bcd digit positions in the bcd accumulator you test the value, and if it's greater than 4 ("100") add 3 ("0011"). Shift, test, conditionally add for all binary bits. Think for loop in a process. –  Jun 13 '14 at 10:33
  • @DavidKoontz I want a code that can be synthesized properly, so I don't wanna use loop, I read somewhere that it gets synthesized but when implemented on a FPGA it is made a counter forcefully, so its a bad practice. That is why I need something with sll and I am having way too much of issues synthesizing sll. How should i shift it left when I cant even get the sll operator work :/ I am lost! – alexhilton Jun 13 '14 at 10:39
  • You can synthesize a loop, honest. Loops are unrolled by synthesis and require a static iteration scheme. See [Convert 8bit binary number to BCD in VHDL](http://stackoverflow.com/questions/23871792/convert-8bit-binary-number-to-bcd-in-vhdl/23872308 "Convert 8bit binary number to BCD in VHDL") for several implementations, including an unrolled loop with minimum hardware. None of these use SLL instead use slices and concatenation or component connectivity. Get a working algorithm simulating first. –  Jun 13 '14 at 11:12

1 Answers1

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What you are doing wrong is, firstly, attempting to debug a design via synthesis.

Write a simple testbench which, first, exercises your design (i.e. given the code above, feeds some data into the X input port).

Later you can extend the testbench to read the Y output port and compare the output with what you would expect for each input, but you're not ready for that yet.

Simulate the testbench and add the entity's internal signals to the Wave window : does the entity do what you expect? If so, proceed to synthesis. Otherwise, find and fix the problem.

The specific lines of code above, y <= x sll 16; and y <= x sll 1; work correctly and the synthesis warnings (NOT errors) are as expected. Shifting a 16 bit number by 16 bits and fitting the result into a 16 bit value, there is nothing left, so (as the warning tells you) port X is entirely unused. Shifting by 1 bit, the MSB falls off the top of the result, again exactly as the warning says.

It is the nature of synthesis to warn you of hundreds of such things (often most of them come from the vendor's own IP, strangely enough!) : if you have verified the design in simulation you can glance at the warnings and ignore most of them. Sometimes things really do go wrong, then one or two of the warnings MAY be useful. But they are not a primary debugging technique; most of them are natural and expected, as above.

As David says, you probably do want a loop inside a clocked process : FOR loops are synthesisable. I have recently read a statement that WHILE loops are often also synthesisable, but I have found this to be less reliable.