Verilog HDL: Using For Loop

Question

Basically I would like to insert a series of repeated blocks (which has logic + registers in it). These blocks will be linked up with one another to form a link.

I tried this code but failed. I just want to your help to point me out, is it my syntax error or I am actually getting to wrong idea speaking from hardware logic wise. Why I keep failing to do so.

module fullchip (dat_out, dat_in, clk);

    output    dat_out;
    input    dat_in, clk;

    //wire    cloud1_out;
    wire [99:0]    cloud_out;
    integer i;
    integer j;

    //combi_logic    cloud1(.combi_out(cloud1_out), .combi_in(dat_in), .clk(clk));
    //combi_logic    cloud2(.combi_out(dat_out), .combi_in(cloud1_out), .clk(clk));

    combi_logic    cloud[0](.combi_out(cloud_out[0]), .combi_in(dat_in), .clk(clk));
    for (i=1; i<99; i=i+1)
    {
    j = i - 1;
    combi_logic cloud[i](.combi_out(cloud_out[i], .combi_in(cloud_out[j]), .clk(clk));
    }
    combi_logic    cloud[99](.combi_out(dat_out), .combi_in(cloud_out[i]), .clk(clk));

endmodule

score 1 · Answer 1 · answered Jun 04 '14 at 17:47

Corrections are in bold (some case extra white-space added to)
Explanations are in italicized comments

module fullchip (dat_out, dat_in, clk);

  output    dat_out;
  input    dat_in, clk;

  wire [99:0]    cloud_out;
  genvar i; // 'integer' to 'genvar'
  // remove 'integer j;'

  generate // required for IEEE1364-2001, optional in IEEE1364-2005 & IEEE1800
  for (i= 0 ; i <= 99; i=i+1) // range [0:99]
  begin // Verilog syntax, not '{' 
    if (i==0)   // cloud[0] --> cloud, for-loop handles indexing 
      combi_logic  cloud(.combi_out(cloud_out[0]), .combi_in(dat_in), .clk(clk));
    else if (i==99)//cloud[99] --> cloud, for-loop handles indexing us
      combi_logic  cloud(.combi_out(dat_out), .combi_in(cloud_out[ i-1 ]), .clk(clk));
    else        // cloud[i] --> cloud, for-loop handles indexing us
      combi_logic  cloud(.combi_out(cloud_out[i] ) , .combi_in(cloud_out[ i-1 ]), .clk(clk));
  end // Verilog syntax, not '}'
  endgenerate // match generate

endmodule

Working example here.

Verilog HDL: Using For Loop

1 Answers1