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How can I bypass caches on all accessed to a certain memory location from user space on ARM?

Here's an example:

uint16_t* ptr = (uint16_t*) malloc(MEM_SIZE * sizeof(uint16_t));

*ptr = 0xFFFF;

Can I make ptr to be uncached to avoid cache pollution? I am running in Syscall Emulation mode (very limited OS support) on an ARMv7 architecture.

UPDATE:

Addressing some of the comments below:

I am running this code on the gem5 simulator (http://www.gem5.org/) in Syscall Emulation mode, which is in short described as follows:

gem5 can simulate a complete system with devices and an operating system in full system mode (FS mode), or user space only programs where system services are provided directly by the simulator in syscall emulation mode (SE mode).

SE mode is using an MMU. I am currently modeling after the ARM Cortex-A9, but I am assuming if there is a way to solve this issue it should be ISA dependent and not processor implementation dependent? I am using L1/L2 caches, but as I am studying various architectures this should also be irrelevant, as I am looking for a general mechanism of bypassing all caches for a specific memory location.

artless noise
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Tayyar R
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  • @artlessnoise Thanks for your comment. I didn't include these details, because I didn't think they will impact the answer in any way. I'm not sure what PSMA is, but I am going to address all your other concerns in an edit to my question. See above. – Tayyar R Jun 04 '14 at 05:40
  • The cache flushing for the ARM is ultimately *processor dependent*. It is done with CP15 registers which are different for Cortex-A vs Cortex-M and even small differences exist between Cortex-A cpus. As well, an MMU table may mark a particular entry as *non-cacheable*. Most likely, the answer is found in the GEM5 source. It may not make sense to emulate the CP15 registers. [Linux armv7 cache code](http://lxr.free-electrons.com/source/arch/arm/mm/cache-v7.S) has examples in `v7_flush_dcache_all`, where the `mcr/mrc` instructions manipulate CP15; values are different per model. – artless noise Jun 04 '14 at 14:03
  • @artlessnoise Thanks! Could you please elaborate on how CP15 is related to marking pages as non-cacheable? – Tayyar R Jun 04 '14 at 17:59
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    Those are two different mechanisms. CP15 is a cache flush/invalidate operation. If the data is in the cache, then it empties. The other mechanism is to mark the memory with the MMU to never be cached (and then you never have to flush). My **major point** is that a real ARM maybe much different than *Gem5 System Emulation mode*. – artless noise Jun 04 '14 at 18:15
  • @artlessnoise Thanks! Yeah, so for what I am doing flushing the cache will not work. But marking the page in the MMU sounds much better. I guess my question is whether there is a proper way to do it on a real ARM platform? Like what would be an instruction sequence, or a function call that would request an uncached memory location from the MMU or the OS? – Tayyar R Jun 06 '14 at 19:09

1 Answers1

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From user space - no. Memory from malloc() comes from the heap.

Through a kernel module, probably yes. Page(s) of memory can be set by MMU as uncached using e.g. dma_alloc_coherent(), then made available to userspace, see LDD3 15.2.7. Remapping Kernel Virtual Addresses. However, that may be more trouble than you wish.

Joe Kul
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  • *in Syscall Emulation mode...* I don't know what that means, but it is not Linux. – artless noise Jun 03 '14 at 22:20
  • Do you think it would be possible to link the source code that contains that primitive to my application, so that the user code could run dma_alloc_coherent? Since this is all simulated, I am assuming the simulator is not super strict about supervisor mode and/or protection. – Tayyar R Jun 04 '14 at 05:50