Casting enum to logic

Question

Consider the following module declaration:

module DFF(d, q, CLK, RESET);
 parameter W = 2;
 input  [W-1:0] d;                      
 input  CLK;                                
 input  RESET;      
 output logic [W-1:0]   q; 

//....
endmodule

What is the proper way of instantiating it where d and q are of enum type? Here is my enum type:

typedef enum logic [1:0] {ENUM_IDLE = 0,
            ENUM_S1 ,
            ENUM_S2
            } T_STATE;

I would like to instantiate the DFF for a T_STATE variable type:

T_STATE d, q;
DFF dff_inst (.d(d), .q(q), .CLK(CLK), .RESET(RESET));

This generates compile/enumeration error. I have also unsuccessfully tried:

DFF dff_inst (.d(logic'(d)), .q(logic'(q)), .CLK(CLK), .RESET(RESET));

and

DFF dff_inst (.d(logic[1:0]'(d)), .q(logic[1:0]'(q)), .CLK(CLK), .RESET(RESET));

I would like to keep the DFF definition as is, but cast the enum type to logic.

Edit:

This one, suggested in IEEE Std 1800-2012, 6.24.1, also generates an elaboration error:

typedef logic [$bits(T_STATE) - 1 : 0] T_STATE_LOGIC; 
DFF dff_inst (.d(T_STATE_LOGIC'(d)), .q(T_STATE_LOGIC'(q)), .CLK(CLK), .RESET(RESET));

Shouldn't you have `input logic [W-1:0] d;` in your definition of DFF? — Mark Lakata, May 27 '14 at 19:20
@MarkLakata, `input logic [W-1:0] d` is legal in SystemVerilog. `logic` has a smaller memory footprint and less over head in simulation compared to `wire`, as `logic` does not have strength information or conflict driver resolution (logic has single driver checked at elaboration when assigned in an `always_comb/ff/latch` block). You'll only see the benefit on very large projects. — Greg, Jun 17 '14 at 01:55

score 4 · Accepted Answer · answered May 27 '14 at 20:08

4

d doesn't need to be casted.

I could only reproduce the error with ModelSim, all the other simulators I have access to didn't generate any errors or warnings and simulated correctly.

For ModelSim, I found that this worked:

DFF dff_inst (.q(q[1:0]), .*);

and this worked:

DFF dff_inst (.q({q}), .*);

Working example on here

answered May 27 '14 at 20:08

Greg

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1

Thanks, it works for me now! Looks like q needs to be converted to an array, right? I thought I needed to convert between the enum type and logic array. – Ari May 27 '14 at 20:33
1

Do you know why the curly braces around `q` are needed and what exactly they do? Do they convert q to an array? I found that even when pin `q` of the flop and the enumerated type are not arrays, the braces are needed. – Ari Jun 16 '14 at 23:33
1

@Ari, the curly bracts treat `q` as an unsigned packed array. Without them, ModelSim see `q` as enum type and treats it as a type conflict (type(enum logic [1:0]) !== type(wire [1:0])). It appears to be a ModelSim bug as `.q(q)`, or just `.*`, work with NC/incisive, VCS, and Icarus – Greg Jun 17 '14 at 01:41

Casting enum to logic

1 Answers1

Linked