I'm currently reading through Irvine 6th ed. to teach myself assembly, and I've come across this sentence on page 277 (section 8.2.2, 'Accessing Stack Parameters', sub-heading 'Passing 8-Bit and 16-Bit Arguments on the Stack'), and it states:
"Though you can push 16-bit operands onto the stack, doing so prevents ESP from being aligned on a doubleword boundary. A page fault may occur and runtime performance may be degraded."
I understand that misaligned memory access can cause performance issues due to the granularity of memory access, but I do not see why a page fault could occur. From my understanding, (hard) page faults occur when an process makes a memory access to a location in virtual memory that is currently not loaded into physical memory.
1. Thus, is the quote saying that the stack might exist in several pages at once, and that the misalignment might make a subsequent memory access go over a page boundary?
2. In the event that I have answered my own question, would allocating the stack size to be exactly the size of one page (i.e., with .STACK 4096 directive in MASM) force the stack to exist contiguously on exactly one page, eliminating this problem? Or might the stack still reside across two different pages?
3. If the latter is true, wouldn't padding the data (which is suggested) still result in a page fault anyway? E.g: If the 16 byte variable is 'val1', and we want to access a dword following it called 'val2', and stack resides in across two pages, with the page aligned to 0x1000:
Before padding After padding
---------------- ----------------
0x1002 | [val1] | 0x1002 | [ PADDING ] |
0x1000 | [val2 high] | 0x1000 | [val1] |
--PG BOUNDARY--- ---PG BOUNDARY--
0x0FFE | [val2 low ] | PG FAULT! 0x0FFE | [val2 high] |PG FAULT!
0x0FFC | [irrelevant] | 0x0FFC | [val2 low ] |
---------------- ----------------
Thank you! (and sorry for all the conditional questions, and if I'm over-thinking this)
