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I have the following code but I don’t know what the 3'bzzz stands for:

`timescale 1ns / 1ps
module reg_tercer_estado(entrada,hab,salida);
input [2:0] entrada;
input hab;
output [2:0] salida;
reg [2:0] auxsalida;

always @(entrada)
begin
    case (hab)
    1'b0: auxsalida=entrada;
    1'b1: auxsalida=3'bzzz;
    endcase
end

assign salida=auxsalida;

endmodule
Greg
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1 Answers1

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According to “HDL Compiler for Verilog” manual, 3'bzzz is 3-bit number, and z is a condition for 'disconnected' or 'high impedance', and it's also is not synthesizable.

So, 3'bzzz means a 3-bit value with all three bits in disconnected state.

toriningen
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    One correction: `z` is synthesizable when declaring tri-state drivers. Example `assign salida = (hab==1'b0) ? entrada : 3'bzzz;` – Greg May 05 '14 at 16:08
  • Thank you, Greg. Frankly saying, answering this question was first time I ever looked at Verilog. – toriningen May 05 '14 at 23:21