I'm trying to pre-load load SDRAM memory to L2 cache. I have initialised the MMU and made 1 translation table. I also enabled the cache and I see the software is using the cache as well...
To load some SDRAM to my L2 cache i tried to work with the Preload Engine (PLE).
I have read the documentation about the PLE but i don't get it to work. This is what i have tried: __asm("MCRR p15,0, %0, %1, c11" : :"r" (0x20000004),"r"(0x20000000)); //program PLE new channel 0x20000004 is the register that contains the start_register value (0x10000000 in my case) 0x20000000 is the register that containts the settings: 0xFFFC007C in my case. This means : Length =16k, stride = 0 and number of blocks is 32 (32 * 16k = 512k which is the amount of L2 cache available)
When I execute this command, the PLE does nothing with the registers PLEIDR, PLEASR, PLEFSR, PLEUAR and PLEPCR. The PLEIDR says that the Fifo_size = 16 and the PLE is available. The PLEASR is always zero which mean the channel is never active The PLEFSR = 16 which means that there are 16 available entries in the FIFO The other settings are user defiened...
What do i have to do to get the PLE channel running?
