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In vhdl, assume I have an unsigned vector defined as follows:

signal s_col_rd_check : unsigned(7 downto 0);

Now, whether I use the following library,

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Or the following

use ieee.numeric_std.all;

Can I use do a comparison between my unsigned vector and an integer value as follows?

some_assignment <= '1' when (s_col_rd_check < 190) else '0';

where 190 is just an integer. Will the above comparison be the same whether I use either one of the libraries?

Thanks, --Rudy

fru1tbat
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Rudy01
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1 Answers1

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The ieee.std_logic_arith and ieee.std_logic_unsigned are proprietary Synopsys packages, and not defined as part of the IEEE VHDL standard. So it is misleading that these packages use the ieee library name, since they are not defined as part of the IEEE standard.

A quick Google search for "std_logic_arith.vhd" yielded at least three different versions of the package, so the answer to your question may depend on which version of the proprietary package your are using... which is a strong indication, that using these proprietary packages is not the right approach, if you want to have well-defined and identical behavior of the design across different tools.

So the reliable approach is to use only the ieee.numeric_std, which is part of the IEEE VHDL standard, thus having well-defined behavior.

And with use ieee.numeric_std.all;, you can do the comparison in:

some_assignment <= '1' when (s_col_rd_check < 190) else '0';

since ieee.numeric_std defines the function:

function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
Morten Zilmer
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    Thanks a lot. I see, and I agree with you 100%. But the problem is that I am stuck with using "std_logic_unsigned", and that is because I am working with an old design developed with someone else. And, I cannot change it to "numeric_std", and that is why I was wondering that using the function will be similar to the "numeric_std" one. – Rudy01 Apr 23 '14 at 20:49
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    Since `ieee.std_logic_arith` is not standardized, I can't answer for the specific package `std_logic_arith` used in your design. However, I have seen a case where `std_logic_arith` and `numeric_std` gives the exact same result for all argument values in the compare, so for the version of `std_logic_arith` I am using, the compare is equivalent. Note that in the case of comparing `unsigned < natural`, the `std_logic_arith` applies, and not the `std_logic_unsigned`, since the latter is for comparing `std_logic_vector < natural` with `std_logic_vector` interpreted as unsigned. – Morten Zilmer Apr 24 '14 at 05:23