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A Similar question was asked but there has been no real answer. Could someone please inform me of a possible way to fix this error?

rocky
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  • Are you using Xilinx? If so, are you trying to run a simulation or are you just trying to synthesize it? – Hugo Apr 13 '14 at 14:48
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    I am using Xilinx and trying to simulate it. Do you know what I should do? – rocky Apr 13 '14 at 14:51
  • To simulate you have to first synthesize the module and then once you know it works you create a test bench for it and double click "Simulate Behavioral Model." – Hugo Apr 13 '14 at 15:15
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    I've done that. It seems to be working fine when synthesising but when I try and simulate it using a test bench, it gives me the error... – rocky Apr 13 '14 at 15:18
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    Look at my post, I found answer: http://stackoverflow.com/questions/23033297/error-in-vhdl-xilinx-failed-to-link-the-design –  Apr 13 '14 at 15:39

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In order to do this, download fuse and place in C:\Xilinx\14.x\ISE_DS\ISE\bin\nt