multiple targets in make file

Question

What does the following rule mean?

$(PROGRAM33).o: $(SYSDIR)/%.o: storeapp%.cpp
                @echo Compiling $< ...

Is it equal to the following

$(SYSDIR)/%.o: storeapp%.cpp
                @echo Compiling $< ...

$(PROGRAM33).o: $(SYSDIR)/%.o

Answer 1

Let's say you have this sort of makefile:

f1.png: d/p1.xml
f2.png: d/p2.xml
f3.png: d/p3.xml

f1.png f2.png f3.png:
    some-interesting-tool $^ -o $@

Here we have chosen to write the shell line only once, listing the dependencies separately.

Since, in this case, the targets (f%.png) are related to their dependencies (d/p%.xml) via (the simple minded) make patterns, we can shorten this boiler-plate thus:

f1.png f2.png f3.png: f%.png: d/p%.png
    some-interesting-tool $^ -o $@

This is a static pattern rule. Much nicer than ordinary pattern rules IMHO. They have the nice property that whatever the % matched in the rule, is available as $* in the recipe.

Note that, not unreasonably, the target pattern must match each of the source files. In your case therefore, each of ${PROGRAM33}.o (probably expands to a single file) must be matched by ${SYSDIR}/%.o.