Need Help Turning off re-align comments after signals in port list. (Verilog-Mode)

Question

Here's my problem, I define a port list as so:

module spi_jstk ( 
                  input        clk,     // System Clock (40MHz)
                  input        reset,   // Async Reset
                  input        START,   // Initialize SPI Transfer
                  input [39:0] DATA,    // Input Data to Transfer
                  input        SS,      // Chip Select
                  output       SCLK,    // Serial Clock
                  input        MISO,    // Master In Slave Out
                  output       MOSI );  // Master Out Slave In

Looks quite nice.

Now lets say I add a new signal to this list or just hit TAB and this is what happens:

module spi_jstk ( 
                  input        clk, // System Clock (40MHz)
                  input        reset, // Async Reset
                  input        START, // Initialize SPI Transfer
                  input [39:0] DATA, // Input Data to Transfer
                  input        SS, // Chip Select
                  output       SCLK, // Serial Clock
                  output       NEW, // NEW SIGNAL
                  input        MISO, // Master In Slave Out
                  output       MOSI );  // Master Out Slave In

Not sure why it did this to my comments, anyone know how I turn off this? Its really frustrating.

Another thing I don't understand is that if I hit TAB on a list of regular signals (not in a port list) it doesn't mess with my comments. These comments stay aligned after tab.

   // Signals
   reg [2:0]  q_state, n_state;
   reg        q_clk;
   reg        q_sck;    //1 MHz ticks
   reg [7:0]  q_mosi;   //1 MHz ticks  
   reg [7:0]  q_miso;   //1 MHz ticks

Anyone know how can I fix this? Thanks.

Answer 1

This seems to be a side-effect of auto-lineup behavior. The documentation of C-hvverilog-auto-lineupenter describes the behavior

Type of statements to lineup across multiple lines.
If 'all' is selected, then all line ups described below are done.

If 'declarations', then just declarations are lined up with any
preceding declarations, taking into account widths and the like,
so or example the code:
    reg [31:0] a;
    reg b;
would become
    reg [31:0] a;
    reg        b;

If 'assignment', then assignments are lined up with any preceding
assignments, so for example the code
    a_long_variable <= b + c;
    d = e + f;
would become
    a_long_variable <= b + c;
    d                = e + f;

However it seems in this process it deletes the extra spaces between the code and the comments, I could not find a way to keep it from messing up with comments (you may want to report a bug to its maintainers do M-xverilog-submit-bug-reportRET). One option might be to disable this behavior by customizing the variable verilog-auto-lineup. There are a couple of ways to do so

1) You can use emacs' customize UI for doing so. Just do M-xcustomize-variableRETverilog-auto-lineupRET. And select the desired value for the variable.

2) You can add one of the following to your init file

(setq verilog-auto-lineup nil)  ;; disable completely

(setq verilog-auto-lineup 'assignment)  ;; disable only for declarations