VHDL MUX select with constant

Question

I have a constant defined in my VHDL package.

constant USE_OSD : integer := 0;

And this is something that I change prior to synthesis in my package. I would like to use this constant as my MUX select line in my VHDL code. How can I do this?

for example, something like:

 s_out <=  path_a WHEN (USE_OSD = 0) else path_b;

Thanks,

--Rudy

You have to add the package to the VHDL file you are working on, with `library work; use work.my_package.all;` — youR.Fate, Mar 14 '14 at 09:17

score 1 · Answer 1 · answered Mar 14 '14 at 11:17

1

This has nothing to do with a MUX select line.

Depending on the value of this constant, this is either elaborated as: s_out <= path_a; or as s_out <= path_b;. There will never be a mux.

As a way of learning, please consider running this through a synthesis tool and looking at the results.

answered Mar 14 '14 at 11:17

Philippe

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The term "mux" may not be accurate, but if the intent is to use a constant to choose between two signal assignments, I don't see anything particularly wrong with this approach. – fru1tbat Mar 14 '14 at 11:57
I agree that there is nothing wrong with the approach. I just wanted to point out that there is no mux inferred. This is in fact a good way to infer _less_ logic. – Philippe Mar 17 '14 at 10:46

score 0 · Answer 2 · answered Mar 14 '14 at 12:00

I think u looking for an if generate. This is like a preprocessor Command in C.

Example:

path_a: if USE_OSD = 0 generate
   s_out <= path_a;
end generate path_a;
path_b: if USE_OSD /= 0 generate
   s_out <= path_b;
end generate path_b;

I think VHDL 2008 also allowse else generate.

VHDL MUX select with constant

2 Answers2