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In a C file file.c I have

#define STUFF

I want a Makefile so that I can prevent STUFF from being defined in file.c. I want to control the compilation using only the Makefile (and I do not want to comment out the line in the .c file directly).

gcc has the -D option. I can do

 gcc -D STUFF file.c -o output

for defining STUFF; but I cannot Undefine STUFF invoking gcc or using the Makefile (with gcc invoked in the Makefile of course).

Any hint ?

erkan
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  • Can you modify the .c file at all? Is it required that STUFF be defined if there is no definition on the command line? – Steve Fallows Mar 13 '14 at 17:00
  • There is a corresponding command to undefine things: `-U`. However, this only undefines values which are already defined at that point, either built-in or from the command line: it doesn't take precedence over things that will later be defined in various files. So if you use `-DFOO -UFOO` then `FOO` is not defined. But you can't undefine something that's `#define`d in a source file from the command line. It would be nice if `-U` worked like an override and ensured that all attempts to `#define` that macro in the source would be ignored. But it doesn't. – MadScientist Mar 13 '14 at 18:10
  • possible duplicate of [how to undefine a define at commandline using gcc](http://stackoverflow.com/questions/1978155/how-to-undefine-a-define-at-commandline-using-gcc) – Beta Mar 14 '14 at 04:40

2 Answers2

6
#define STUFF

#ifdef REMOVE_STUFF
#undef STUFF
#endif

Then compile with gcc -DREMOVE_STUFF ...

pmg
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2

You need to change file.c, you can't do this without changing the source file. e.g. make it:

#ifdef ENABLE_STUFF
#define STUFF
#endif

And have your makefile add the -DENABLE_STUFF flag

nos
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  • But in this case STUFF will not be defined for a compile with no command line definition, which seems to be a requirement (the question is a little unclear on that). – Steve Fallows Mar 13 '14 at 16:54